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Method for Lithographic Tool and Process Characterization

IP.com Disclosure Number: IPCOM000042467D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Rottmann, HR: AUTHOR [+2]

Abstract

The ever decreasing feature sizes of semiconductor devices make it essential to fully understand the capabilities and limitations of various types of lithographic tools and processes. State-of-the-art lithographic tools including scanning projection systems, direct wafer steppers, and E-beam systems all have their unique individual characteristics and limitations. Disclosed herein is a method for lithographic tool and process characterization, using an offset multiple-exposure technique and a specially designed test mask. This method permits isolation of various process and tool parameters, uses the same wafer for offset re-exposures to minimize the number of water samples required, and can be applied to scanning projection lithography systems and to direct wafer stepper systems to permit a comparison of system capabilities.

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Method for Lithographic Tool and Process Characterization

The ever decreasing feature sizes of semiconductor devices make it essential to fully understand the capabilities and limitations of various types of lithographic tools and processes. State-of-the-art lithographic tools including scanning projection systems, direct wafer steppers, and E-beam systems all have their unique individual characteristics and limitations. Disclosed herein is a method for lithographic tool and process characterization, using an offset multiple-exposure technique and a specially designed test mask. This method permits isolation of various process and tool parameters, uses the same wafer for offset re- exposures to minimize the number of water samples required, and can be applied to scanning projection lithography systems and to direct wafer stepper systems to permit a comparison of system capabilities. Figs. 1-4 illustrate the details of the test mask design. Fig. 1 shows a 10x10 image array on a wafer. Fig. 2 shows the overall single cell design of the test pattern which consists of a variable width line/space resolution "L" pattern and a "cross" alignment target pattern. The variable width line/space resolution "L" pattern is shown in Fig. 3. It consists of 15 resolution segments of different widths in two orthogonal (x and y) directions. Each segment includes lines with both equal spacings and double spacings for adjacency studies. Also included in each segment is a square of the...