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Digitally Controlled Pulse-Width Generation

IP.com Disclosure Number: IPCOM000042469D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 30K

Publishing Venue

IBM

Related People

Johnson, DA: AUTHOR

Abstract

A pulse generating circuit directly translates a digital value into the width of a single pulse, where the range of pulse-width variation is large. A strobe pulse (Fig. 2) is applied to terminal 5 (Fig. 1) to initiate the pulse to be generated. The pulse loads decrementing counter 20, sets output latch 80, and fires single-shot 60 through OR gate 70. The generated pulse of the single-shot 60 is fed to programmable delay line (PDL) 30. The programmable delay line 30 can delay a pulse from input to output in programmable increments set by "b" bits where the total possible delay is (2b-1)*D, where D is the increment of delay for each step and b and D are dependent on the type of PDL used. The delayed pulse from PDL 30 feeds the countdown clock input of countdown counter 20.

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Digitally Controlled Pulse-Width Generation

A pulse generating circuit directly translates a digital value into the width of a single pulse, where the range of pulse-width variation is large. A strobe pulse (Fig. 2) is applied to terminal 5 (Fig. 1) to initiate the pulse to be generated. The pulse loads decrementing counter 20, sets output latch 80, and fires single-shot 60 through OR gate 70. The generated pulse of the single-shot 60 is fed to programmable delay line (PDL) 30. The programmable delay line 30 can delay a pulse from input to output in programmable increments set by "b" bits where the total possible delay is (2b-1)*D, where D is the increment of delay for each step and b and D are dependent on the type of PDL used. The delayed pulse from PDL 30 feeds the countdown clock input of countdown counter 20. If no high- order data bits are set in width control register 10, counter 20 is at zero. The occurrence of the pulse from PDL 30 causes counter 20 to drop borrow line 21. The fall of borrow line 21, which is the stop pulse, resets output latch 80 via OR circuit 90. In the case of high-order bits, the pulse-width range is from 0 to (K - 1)*D plus some small minimum width. K is the maximum value of the low-order bits plus one (K=2b). In the case of high-order bits present, counter 20 is decremented at the occurrence of the pulse from PDL 30, but no borrow occurs as the counter 20 is not zero. The pulse from PDL 30 also feeds another PDL
40. The delay for PDL 40 is set by a function dependent on the value of the low- order bits N in width control register 10. Two cases of f(N), ones complement and twos complement are considered herein. AND gate 45 allows circulation only while output latch 80 has been set. Therefore, the stop pulse from counter 20 also prevents further circulation in the loop. The stop/clear control signal applied to terminal 95 allows interruption of an output pulse and can prevent any response to a strobe pulse while held active. The time for a pulse to travel from single-shot 60 around the loop of PDL 30, PDL 40, OR circuit 70, AND circuit 45, and back to single-shot 60 is called circulation time. Circulations of the loop are counted by counter 20. The circulation time can be expressed mathematically as: Equation 1 Tc = delay PDL 30 + delay PDL 40 + delay OR circuit 70, AND circuit 45 + delay single-shot 60 propagation = D * N + d1 + D * (f(N)) + d1 + d2 + d3 = D * (N + f(N)) + 2d1 + d2 + d3 where K is the modulus of the low-order bits (K = 2b, where b is the number of low-order bits) D is the increment of delay in the PDL N is the value of the low-order bits d1 is the delay in PDL 30 and PDL 40 when N=0 d2 is propagation delay through single-shot 60 d3 is the block delay in AND 45 and OR 70. In the case where f(N) = [twos complement of N] = K - N (modulo K) (Fig. 3), the circulation time, Tc, becomes expressed as follows: Tc = D * (N + (K - N)) + 2d1 + d2 + d3 = D * (N + K - N) + 2d1 + d2 + d3 Equation...