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Selective Testing of Lines and Interconnection Circuitry

IP.com Disclosure Number: IPCOM000042473D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Rausch, F: AUTHOR

Abstract

Lines from a chip on a first circuit card to a chip on a second circuit card are particularly susceptible to defects, as they comprise at least four soldered joints and two plug connectors. At present, the quality of such joints and connectors cannot be tested as economically as would be desirable. If individual control or clock signals, rather than parity-checked bus connections, are concerned, errors or defects are particularly difficult to detect and localize. The circuit arrangement described below is used for improved error detection and error localization. The figure shows two circuit cards 1 and 2, on each of which two chips 4, 5 and 6, 7, respectively, are arranged. Line groups 8, 9, 10 and 11 connect the circuits of the respective chips to circuits on chips of other cards.

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Selective Testing of Lines and Interconnection Circuitry

Lines from a chip on a first circuit card to a chip on a second circuit card are particularly susceptible to defects, as they comprise at least four soldered joints and two plug connectors. At present, the quality of such joints and connectors cannot be tested as economically as would be desirable. If individual control or clock signals, rather than parity-checked bus connections, are concerned, errors or defects are particularly difficult to detect and localize. The circuit arrangement described below is used for improved error detection and error localization. The figure shows two circuit cards 1 and 2, on each of which two chips 4, 5 and 6, 7, respectively, are arranged. Line groups 8, 9, 10 and 11 connect the circuits of the respective chips to circuits on chips of other cards. For selection, each chip is provided with as many bilateral switches 12 as there are lines to be tested. Each of these switches is associated with one shift register latch (SRL). SRL chains 13, 14, 15 and 16 are obtained by combining the SRLs. For each card, the outputs of switches 12 are interconnected, forming one common line 17, 18, 19,
20. A logical l-signal at the output of one SRL connects the input of the associated switch 12 to the common output. Given suitable packaging, the SRLs existing on the cards can be used for switch control purposes. In such cases, a central signal (not shown) ensures that undesirable line coupli...