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Gated Data Latch in I2L

IP.com Disclosure Number: IPCOM000042475D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

A gated data latch is a basic element in logic design. In I2L a straightforward approach is illustrated in Fig. 1. A simplified circuit configuration of an I2L gated data latch is shown in Fig. 2. In this circuit the clock C is not "dotted" with the data input D, but is employed as a variable circuit bias. Thus multiple fanouts for the clock C are possible. Also, as illustrated in Fig. 3, the latch of Fig. 2 may be readily extended to provide a static DC cell for a two-port RAM.

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Gated Data Latch in I2L

A gated data latch is a basic element in logic design. In I2L a straightforward approach is illustrated in Fig. 1. A simplified circuit configuration of an I2L gated data latch is shown in Fig. 2. In this circuit the clock C is not "dotted" with the data input D, but is employed as a variable circuit bias. Thus multiple fanouts for the clock C are possible. Also, as illustrated in Fig. 3, the latch of Fig. 2 may be readily extended to provide a static DC cell for a two-port RAM.

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