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Hardware Assist for Device Re-Entrant Microcode

IP.com Disclosure Number: IPCOM000042480D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Sibbers, DE: AUTHOR

Abstract

The present trend of migrating system function to input/output (I/O) controllers in Data Processing systems requires careful tradeoffs between I/O controller hardware and software. In a typical controller, use of relatively simple hardware additions improved the efficiency of the microcode allowing the use of a simple, low-cost microprocessor without sacrificing controller performance. Such an I/O controller that provides high-level control for a plurality of hard files has dedicated hardware for high-speed data channel operations with low-speed functions and primary control provided by a special-purpose microprocessor. The controller provides full overlapped operations for a plurality of files, such as four, except that only one file can transmit data at a time.

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Hardware Assist for Device Re-Entrant Microcode

The present trend of migrating system function to input/output (I/O) controllers in Data Processing systems requires careful tradeoffs between I/O controller hardware and software. In a typical controller, use of relatively simple hardware additions improved the efficiency of the microcode allowing the use of a simple, low-cost microprocessor without sacrificing controller performance. Such an I/O controller that provides high-level control for a plurality of hard files has dedicated hardware for high-speed data channel operations with low-speed functions and primary control provided by a special-purpose microprocessor. The controller provides full overlapped operations for a plurality of files, such as four, except that only one file can transmit data at a time. The control strategy is based on device re-entrant microcode which allows multiple devices of the same type to concurrently use a single set of code without causing interaction between devices. The additional hardware used to improve the efficiency of this control strategy implements the following functions: 1. A device encode register. 2. Use of the device encode register to select 1 of N devices. 3. Placement of command and status information using the device encode as part of the address.
4. Microprocessor instructions to access buffer storage using the device encode register for indexing. 5. Hardware save of the device encode register during interrupts or branch and link (subroutine call) instructions. 6. Hardware restore of device encode register during a return instruction or when an exit interrupt level occurs. 7. Access to information hardware saved by an interrupt or branch and link. 8. Microprocessor instruction to resolve multiple service requests and load the device encode register. To illustrate the use of these hardware functions, a brief explanation of their use in the above-referenced typical controller follows. The controller uses a 256-byte portion of a 1024-byte buffer for communication of command and status information to the system. Since only 128 bytes are required for a four-file system, the other 128 bytes are used by the processor for local store and work area. The layout is shown in Fig. 1. Command and status information is transferred to and from the system by a hardware sequence. The file encode is used to form the 128- and 64-weight binary address. This provides Function 3. The device encode register resides in the processor chip. The outputs of the register are brought to output pins which are used to select one of four files when sending control/sense commands to an individual file. Internal to the processor, the file encode register may be used to index accesses to buffer data. The indexing consists of simply ORing the register into the 128- and 64-weight binary positions of the buffer...