Browse Prior Art Database

Bus Extension System

IP.com Disclosure Number: IPCOM000042497D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Yanagi, T: AUTHOR

Abstract

Disclosed is a bus extension system which is capable of bidirectionally coupling a basic bus and an extended bus without using a dedicated control circuit on each functional card attached thereto, but using a single bus extension card interposed between the basic bus and the extended bus. The present bus extension system does not require any termination card which has been customarily used in the prior systems to terminate the basic or extended bus at its remote end. Referring to Fig. 1, there is shown the bus extension card interposed between the basic bus and the extended bus, each being adapted for bidirectionally transferring address, data and control signals.

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Bus Extension System

Disclosed is a bus extension system which is capable of bidirectionally coupling a basic bus and an extended bus without using a dedicated control circuit on each functional card attached thereto, but using a single bus extension card interposed between the basic bus and the extended bus. The present bus extension system does not require any termination card which has been customarily used in the prior systems to terminate the basic or extended bus at its remote end. Referring to Fig. 1, there is shown the bus extension card interposed between the basic bus and the extended bus, each being adapted for bidirectionally transferring address, data and control signals. Among the functional cards attached to these buses, either the microprocessor unit (MPU) and or the direct memory access controller (DMAC l-2) behaves as a bus master at a given time. Thus, it is required to generate an interlocking signal for coordinating activities of these possible bus masters in addition to the so-called direction indicating signal. As seen from the following, all of these signals are handled by the bus extension card per se without recourse to any dedicated control circuit on each bus master. A block diagram of the bus extension card is shown in Fig. 2, which for simplicity illustrates a direction control circuit and a bus drive circuit associated with the address signals only. The input signals to the direction control circuit are Basic Address Enable (BAEN), which is provided from DMAC-1 for enabling driver A in Fig. 2, and Extended Address Enable (EAEN), which is provided from DMAC-2 for enabling driver B in Fig. 2. The signal supplied from the direction control circuit to the bus drive circuit is Extended Address Enable Select (EAENSEL), which is provided to driver A' or B' to determine the direction the address signals are to be passed through the bus drive circuit. During the operation of the bus extension card, the BAEN and EAEN signals should be supplied in three different combinations depending on which of DMAC-1, DMAC-2 and MPU is acting as the current bus master. For example, when DMAC-1 is acting as the bus master, the BAEN signal must be active (low level) and the EAEN signal must be inactive (high level). In this case, driver A is enabled by the activated Basic Address Enable Selec...