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Terminal Communications Adapter

IP.com Disclosure Number: IPCOM000042507D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Satoh, N: AUTHOR

Abstract

This article describes a terminal communications adapter for an intelligent terminal employing a microprocessor. The adapter is provided with a two-port memory for buffering data. The memory is accessed by the adapter itself and the microprocessor. This adapter is useful to perform high speed data communication without causing overruns and/or communication response errors which occur in conventional arrangements having no two-port memory and employing the DMA or interruption techniques. As shown in Fig. 1, the terminal 1 includes a terminal communications adapter (TCA) 2 which is provided with a two- port memory 4. The TCA 2 has means (not shown) for accessing the memory 4 when it receives or transmits data from or to a communication line 7.

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Terminal Communications Adapter

This article describes a terminal communications adapter for an intelligent terminal employing a microprocessor. The adapter is provided with a two-port memory for buffering data. The memory is accessed by the adapter itself and the microprocessor. This adapter is useful to perform high speed data communication without causing overruns and/or communication response errors which occur in conventional arrangements having no two-port memory and employing the DMA or interruption techniques. As shown in Fig. 1, the terminal 1 includes a terminal communications adapter (TCA) 2 which is provided with a two- port memory 4. The TCA 2 has means (not shown) for accessing the memory 4 when it receives or transmits data from or to a communication line 7. Also, a microprocessor (MPU) 5 can access the memory 4 as if it were a part of a main memory 6. A control logic 3 controls the access timing of the TCA 2 and the MPU 5 for the memory 4. When TCA 2 wants to access the memory 4, the logic 3 raises the TCA Memory Select signal, as shown in Fig. 2, in the middle of Adapter Control Clock pulse to allow the TCA 2 to access the memory 4. The TCA Memory Select signal remains high until the leading edge of the next Clock pulse. If the MPU 5 wants to access the memory 4, the logic 3 raises the MPU Memory Select signal at the trailing edge of the Clock pulse after the TCA Memory Select signal has dropped. The MPU Memory Select signal remains high until th...