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Using a Shift Register to Generate Verification Tests

IP.com Disclosure Number: IPCOM000042510D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 24K

Publishing Venue

IBM

Related People

Carter, WC: AUTHOR

Abstract

Presently, verification tests are generated using the single stuck fault hypothesis. The Level Sensitive Scan Design (LSSD) latch circuits on a chip are connected in a shift register, and a verification test is read into the latches one bit at a time. The test is run in one cycle, the result examined, and the next test then read-in. This is time consuming and not at full machine speed. With the technique described below, the LSSD latches are connected to form a Non-Linear Feedback Shift Register (NLFSR), the outputs of which are themselves the generated verification tests. The tests are generated and applied at full machine speed. The tests may be evaluated bit by bit, or the results may be compacted using a LFSR and a signature analyzed. Let X be a vector with n components over GF(2):X0,X1,..Xn-1.

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Using a Shift Register to Generate Verification Tests

Presently, verification tests are generated using the single stuck fault hypothesis. The Level Sensitive Scan Design (LSSD) latch circuits on a chip are connected in a shift register, and a verification test is read into the latches one bit at a time. The test is run in one cycle, the result examined, and the next test then read-in. This is time consuming and not at full machine speed. With the technique described below, the LSSD latches are connected to form a Non- Linear Feedback Shift Register (NLFSR), the outputs of which are themselves the generated verification tests. The tests are generated and applied at full machine speed. The tests may be evaluated bit by bit, or the results may be compacted using a LFSR and a signature analyzed. Let X be a vector with n components over GF(2):X0,X1,..Xn-1. Represent the next state of the NLFSR by

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where Yi is a n element vector with components in GF(2); Bi is a Boolean function of X0, X1,..,Xn-1, and E is the next state operator for a LFSR. By choosing the values of the Bi and Yi, the outputs X0,..Xn-1 will generate the elements of a verification test. The procedure is illustrated by the following example; then the method designing the NLFSR will be described in general. Consider the combinatorial function shown in the figure. The verification tests are:

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Test a b c d (1) 0 0 1 1 (2) 1 1 0 1 (3) 0 0 0 1 (4) 1 1 0 0 (5) 1 0 0 0 The 4-Stag...