Browse Prior Art Database

Low Voltage Power Supply Leakage Test

IP.com Disclosure Number: IPCOM000042532D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Adams, JH: AUTHOR [+3]

Abstract

This article describes a method for measuring the N-channel leakage (between adjacent subcollectors across P-isolation under the recessed oxide isolation (ROI)). This method was developed for products on which there are no closely spaced adjacent devices available on the chip pads. In situations where large charges are present in the oxide and/or the isolation diffusion doping is light near the ROI, an N-channel leakage path may be formed below the ROI. This path could cause testing problems at the next level of assembly. Tests were developed to measure this leakage on products with adjacent closely spaced devices on their inputs or outputs as available on two of our ROI products. Others did not have such structures available on the product to permit direct measurement of N-channel leakage.

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Low Voltage Power Supply Leakage Test

This article describes a method for measuring the N-channel leakage (between adjacent subcollectors across P-isolation under the recessed oxide isolation (ROI)). This method was developed for products on which there are no closely spaced adjacent devices available on the chip pads. In situations where large charges are present in the oxide and/or the isolation diffusion doping is light near the ROI, an N-channel leakage path may be formed below the ROI. This path could cause testing problems at the next level of assembly. Tests were developed to measure this leakage on products with adjacent closely spaced devices on their inputs or outputs as available on two of our ROI products. Others did not have such structures available on the product to permit direct measurement of N-channel leakage. For these products an in- process test (IPT) was implemented to reject, at IPT, all wafers that have at least one fail out of 32 sites for N-channel leakage. This resulted in many wafers being rejected, most of which had only small localized regions of leakage on them. The idea presented in this article is a new test which would test all products not having closely spaced adjacent structures available on the chip pads at final device test. This test is a low voltage-leakage test between the VCC and VEE power pads. It makes the VEE more positive than VCC by a small amount which forward biases the isolation - subcollector p-n junction. (On all R...