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Browse Prior Art Database

FET Bias Networks With Feedback

IP.com Disclosure Number: IPCOM000042537D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Cheung, SK: AUTHOR [+4]

Abstract

The feedback networks shown in Figs. 1 and 2 can be designed to generate a tight tolerance low voltage reference required for standard T2L level compatible FET address buffers. The networks provide dynamic voltage adjusting via feedback to reduce injected noise. Devices 2, 3, and 4 provide the primary feedback and the drive currents for stabilizing downgoing noise. Devices 1, 1B, 5 and 7 provide additional feedback and the drive current for stabilizing upgoing noise.

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FET Bias Networks With Feedback

The feedback networks shown in Figs. 1 and 2 can be designed to generate a tight tolerance low voltage reference required for standard T2L level compatible FET address buffers. The networks provide dynamic voltage adjusting via feedback to reduce injected noise. Devices 2, 3, and 4 provide the primary feedback and the drive currents for stabilizing downgoing noise. Devices 1, 1B, 5 and 7 provide additional feedback and the drive current for stabilizing upgoing noise.

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