Browse Prior Art Database

Submicron IGFET Device With Double Implanted Lightly Doped Drain/Source Structure

IP.com Disclosure Number: IPCOM000042540D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Codella, CF: AUTHOR [+2]

Abstract

Description An improved version of the LDD FET [1] suitable for submicron channel length operation has been provided. The new structure (DI-LDD) in Fig. 1 improves short channel threshold fall-off to the point that half micron (or shorter) channel lengths are possible while maintaining the LDD advantages in breakdown and resistance to hot electron gate instability. The structure introduces a p-pocket under the narrow self-aligned n region between the channel and the n+ source/drain diffusions. The role of the p-pocket is the prevention of punch-through, which is the mirror image of VT fall-off. The p-pocket reduces the width of the depletion region at the drain junction, thereby protecting the device from punching through the relatively low impurity concentration of the bulk region between the source and drain.

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Submicron IGFET Device With Double Implanted Lightly Doped Drain/Source Structure

Description An improved version of the LDD FET [1] suitable for submicron channel length operation has been provided. The new structure (DI-LDD) in Fig. 1 improves short channel threshold fall-off to the point that half micron (or shorter) channel lengths are possible while maintaining the LDD advantages in breakdown and resistance to hot electron gate instability. The structure introduces a p-pocket under the narrow self-aligned n region between the channel and the n+ source/drain diffusions. The role of the p-pocket is the prevention of punch-through, which is the mirror image of VT fall-off. The p- pocket reduces the width of the depletion region at the drain junction, thereby protecting the device from punching through the relatively low impurity concentration of the bulk region between the source and drain. The p-pocket is designed to minimize its out-diffusion to the surface, in order that the threshold may still be determined by the conventional boron channel implant prior to polysilicon gate definition. This also avoids increasing the impact ionization at the surface and distinguishes the DI-LDD structure from the previous DSA (double-diffused self-aligned) FET structure [2]. An option of this structure is the p-type polysilicon gate with an n skin channel implant which behaves as an enhancement-type device and provides an improved electron mobility. Otherwise, the mobility improvement will never be realized in the conventional half micron (or less) device due to the deteriorated short channel effects resulting fro...