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Paging Eligibility for Hierarchic Design Verification Applications

IP.com Disclosure Number: IPCOM000042578D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Cheng, DD: AUTHOR [+3]

Abstract

Hierarchic design verification applications use a flag for each hierarchic node, to control paging in a manner that will handle large model applications requiring paging without penalizing small model applications requiring no paging. Traditionally, software paging schemes used by applications result in numerous checks and/or assignments done within the application itself to alleviate model limits imposed by the availability of virtual storage. These extra instructions normally execute, even when the design model is not affected by storage limitations. That is, the small model user is penalized for the sake of the large model user. The technique described below reduces this penalty to a bare minimum level, while maintaining the advantages of an application using a software paging scheme for processing large hierarchic models.

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Paging Eligibility for Hierarchic Design Verification Applications

Hierarchic design verification applications use a flag for each hierarchic node, to control paging in a manner that will handle large model applications requiring paging without penalizing small model applications requiring no paging. Traditionally, software paging schemes used by applications result in numerous checks and/or assignments done within the application itself to alleviate model limits imposed by the availability of virtual storage. These extra instructions normally execute, even when the design model is not affected by storage limitations. That is, the small model user is penalized for the sake of the large model user. The technique described below reduces this penalty to a bare minimum level, while maintaining the advantages of an application using a software paging scheme for processing large hierarchic models. A logic design which is structured from a high to a low level is called a top-down design, and the corresponding design model is called a hierarchic model. A top-down design begins with a high level description of the entire system being designed. This high-level description is divided into components to form a lower-level design. These components can be broken-down further in order to form an even lower- level design. In this manner, a hierarchic model is formed. Each component in the model is called a hierarchic node. Thus, each node is a basic "building block" in the logic design. The technique involved is to demand all required tables for a hierarchic node in the model when that node needs to be analyzed. "To demand" is to require all tables to be at known addresses in main storage, as opposed to residing on disk. These tables would...