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Two-Bit Cascadable Counter With Single Gate Delay Per Bit

IP.com Disclosure Number: IPCOM000042583D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Tibbitts, SA: AUTHOR

Abstract

A high speed up-down counter is provided which can be cascaded to any number of bit positions. It is specifically suited for use in gate array technologies with inverting gates only and mixed rail outputs on the latches. Ripple carry counters are generally more efficient in terms of gate count than fully parallel versions. Ripple carry counters with a large number of bit positions are inherently slower than parallel counters of the same dimensions. The present counter is a fast-ripple cascadable up-down counter with only a single gate delay for each additional bit. Any systems clocks that obey level sensitive scan design (LSSD) rules may be used to clock the L1-L2 latches shown in the drawing.

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Two-Bit Cascadable Counter With Single Gate Delay Per Bit

A high speed up-down counter is provided which can be cascaded to any number of bit positions. It is specifically suited for use in gate array technologies with inverting gates only and mixed rail outputs on the latches. Ripple carry counters are generally more efficient in terms of gate count than fully parallel versions. Ripple carry counters with a large number of bit positions are inherently slower than parallel counters of the same dimensions. The present counter is a fast-ripple cascadable up-down counter with only a single gate delay for each additional bit. Any systems clocks that obey level sensitive scan design (LSSD) rules may be used to clock the L1-L2 latches shown in the drawing. The inputs to the counter 10 are INCR (increment) and DECR (decrement); these are positive active lines which control the operations of the counter. A 1 on the INCR line 15 causes counter 10 to add 1 to its contents, while a 1 on the DECR line 20 causes counter 10 to subtract 1 from its contents. If INCR and DECR are both active, counter 10 will toggle both bits. The output lines INCR CARRY 30 and DECR CARRY 35 are also positive active and are designed to connect directly to the inputs of the next stage INCR and DECR, respectively. DA and DB lines 50 and 55, respectively, are the positive data outputs of the L2 latches 40 and 45. The important feature is to recognize the critical path from the inputs INCR and DECR to...