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Circuit to Control the Time Rate of Change of Current at the Output Node of an Off-Chip Driver

IP.com Disclosure Number: IPCOM000042601D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Stoops, EH: AUTHOR

Abstract

The object of the invention is to control the time rate of change of current passing through the active device in the output stage of an FET off-chip driver circuit, while maintaining the maximum current conducting capability of the active device. The figure shows the off-chip driver (OCD) circuit which has five inverter stages feeding into an output totem pole circuit 25. A first stage, consisting of the FET devices 1 and 2, and a second stage, consisting of the FET devices 19 and 20, have their respective active device gates connected to the input node which receives signals from the internal circuitry on a VLSI chip. The output node of the first stage is applied to the load devices 5 and 5D of the gate control circuit 15.

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Circuit to Control the Time Rate of Change of Current at the Output Node of an Off-Chip Driver

The object of the invention is to control the time rate of change of current passing through the active device in the output stage of an FET off-chip driver circuit, while maintaining the maximum current conducting capability of the active device. The figure shows the off-chip driver (OCD) circuit which has five inverter stages feeding into an output totem pole circuit 25. A first stage, consisting of the FET devices 1 and 2, and a second stage, consisting of the FET devices 19 and 20, have their respective active device gates connected to the input node which receives signals from the internal circuitry on a VLSI chip. The output node of the first stage is applied to the load devices 5 and 5D of the gate control circuit
15. The input node for the OCD circuit is connected to the gate of the active FET device 6 in the gate control circuit 15. The signal on output node ND2 of the gate control circuit 15 is applied to the gate of the active FET device 18 in the pair of devices 17 and 18 in the output totem pole circuit of the OCD. The output node OUT is connected to the output pad on the VLSI chip. A problem which arises in state-of-the-art VLSI chip packages is that the ground path and the drain voltage path for the off-chip driver circuits must connect through a relatively large inductance L in the form of off-chip wiring, for example, in connecting the VLSI chip to its surrounding environment. When the OCD circuit rapidly switches on currents which flow through its output node and through either its ground path or its drain voltage path, the back EMF from the inductance L in those respective paths will effect the potential of the output node for the circuit. This has the adverse effect of minimizing the average voltage swing at the output node of the OCD circuit. It has the further adverse effect of altering the effective ground reference potential for other circuits on the VLSI chip which may be sensitive to such variations. And still further, spurious up-level signals can be applied to otherwise qu...