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ROM Sense Bus

IP.com Disclosure Number: IPCOM000042602D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Beha, H: AUTHOR

Abstract

Controlling a sense bus gate by two input signals of opposite polarity permits the use of a simple single-gate-per-bit-sensing circuit in a Josephson read-only memory (ROM). The basic new sense bus structure for a ROM is shown in Fig. 1, having a sense bus gate, which is controlled by two input signals IS and ID, with opposite polarity. The sense bus gate is an asymmetric two-junction interferometer, whereby the DC-string current ISBCD is inserted directly at the smaller Josephson junction, resulting in the threshold characteristic shown in Fig. 2. The pulse sequence during sensing is shown in Fig. 3. Prior to sensing, the ISBDC and the sense current IS are applied, resulting in an operating point A (Fig. 2). After the application of the current ID the sense bus gate is in the operating point B.

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ROM Sense Bus

Controlling a sense bus gate by two input signals of opposite polarity permits the use of a simple single-gate-per-bit-sensing circuit in a Josephson read-only memory (ROM). The basic new sense bus structure for a ROM is shown in Fig. 1, having a sense bus gate, which is controlled by two input signals IS and ID, with opposite polarity. The sense bus gate is an asymmetric two-junction interferometer, whereby the DC-string current ISBCD is inserted directly at the smaller Josephson junction, resulting in the threshold characteristic shown in Fig.
2. The pulse sequence during sensing is shown in Fig. 3. Prior to sensing, the ISBDC and the sense current IS are applied, resulting in an operating point A (Fig. 2). After the application of the current ID the sense bus gate is in the operating point B. Reading of a "1" of the ROM cell causes the sense current IS to decay, which causes the current trajectory to exceed threshold (point C). Consequently, the sense bus gates sensing a "1" switch to the voltage state, transferring the current ISB in the output loop. In order to avoid multiple switching of the sense bus gate, the timing of the signals has to be chosen in the following way: a) The current ID stays switched on after the sensing operation (Fig. 3). Then the sense line current IS has to be reestablished before the current ISB is retransferred. b) The current ID is switched off after the sensing operation. Then the sense bus current ISBDC can be tran...