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Method of Checking Print Band Velocity

IP.com Disclosure Number: IPCOM000042605D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Bloom, RD: AUTHOR [+3]

Abstract

Print band velocity must be maintained within preset limits to insure good print quality. The method determines if the band speed is within the allowable velocity limits, and forces speed checks if the speed is out of tolerance. The method uses a microprocessor and speed check logic which is programmable for operation over a wide range of speeds. As seen in the data flow diagram of Fig. 1, the system for checking print band velocity comprises microprocessor (MPU) 10 and speed check logic 11. Timing marks on type band 12 are sensed by transducer 13. Emitter pulses produced by transducer 13 are supplied through amplifier 14 and phase-locked oscillator 15 which generates pulses indicative of the velocity of band 12. Timing is provided by system clock 16 that is common to MPU 10 and check logic 11.

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Method of Checking Print Band Velocity

Print band velocity must be maintained within preset limits to insure good print quality. The method determines if the band speed is within the allowable velocity limits, and forces speed checks if the speed is out of tolerance. The method uses a microprocessor and speed check logic which is programmable for operation over a wide range of speeds. As seen in the data flow diagram of Fig. 1, the system for checking print band velocity comprises microprocessor (MPU) 10 and speed check logic 11. Timing marks on type band 12 are sensed by transducer 13. Emitter pulses produced by transducer 13 are supplied through amplifier 14 and phase-locked oscillator 15 which generates pulses indicative of the velocity of band 12. Timing is provided by system clock 16 that is common to MPU 10 and check logic 11. When check logic 11 determines a velocity outside the limits of a selected velocity, it initiates a speed check by generating an interrupt (IRQ) to MPU 10. In response to the IRQ, MPU 10 accesses check logic 11 via data bus 17 and I/O register 18 to determine the error. Three bits in I/O register 18 from MPU 10 enable and control velocity checking by check logic
11. As seen in the logic diagram of Fig. 2, the logic elements of check logic 11 and their function are as follows: Edge Detector 19 - detects the leading edges of successive incoming pulses from phase-locked oscillator 15 and generates sample and reset pulses to condition the logic and establish the time interval for measuring velocity. Counter 20 - an elapsed time counter, conditioned by a reset pulse from edge detector 19 for counting timing pulses from system clock 16, measures the period between pulses from the phase-locked oscillator 15. Decode 21 - decodes the full count condition of counter 20 and provides a full count signal to set band slow latch 22. Data Register 23 - stores velocity data received from MPU 10 defining fast velocity limits. Data Register 24 - stores velocity data received from MPU 10 defining slow velocity limits. Comparator 25 - compares the elapsed time data of counter 20 with the fast velocity data stored in register 23. If the compared data are equal, sets latch 27 for making either a print inhibit or speed check at the fast speed. Comparator 26 - compares the elapsed time data of counter 20 with the slow velocity data stored in register 24. If the compared data are equal, sets latch 28 for making either a print inhibit or speed check at the slow speed. Print Inhibit Check Latch 31 - set when the velocity of the band 12 exceeds the limit stored in data register 23 or 24. When set, generates an IRQ to MPU 10 and stores an inhibit bit in sense register 29. Speed Check Latch 30 - set when velocity of band 12 exceeds the limit stored in data register 23. Generates an IRQ if set to MPU 10...