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Browse Prior Art Database

Output Noise Compensation Circuit

IP.com Disclosure Number: IPCOM000042620D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Stoops, EH: AUTHOR

Abstract

The figure shows an FET off-chip driver (OCD) circuit. The invention is the inverter circuit 15 comprising the three devices 13, 13D and 14. FET device 13 is a natural threshold device, FET device 13D is a depletion-mode FET device, and FET device 14 is an enhancement-mode FET device. The gates of the load FET devices 13 and 13D are connected in common. A positive signal at the input passes through the pair of cascade-connected inverters formed by devices 19, 20, 9 and 10 and is applied as a positive signal to the gates of devices 13 and 13D. The positive signal at the input passes through the pair of push-pull connected inverters 1, 2, 5 and 6 and is applied as a negative signal to the gate of device 14.

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Output Noise Compensation Circuit

The figure shows an FET off-chip driver (OCD) circuit. The invention is the inverter circuit 15 comprising the three devices 13, 13D and 14. FET device 13 is a natural threshold device, FET device 13D is a depletion-mode FET device, and FET device 14 is an enhancement-mode FET device. The gates of the load FET devices 13 and 13D are connected in common. A positive signal at the input passes through the pair of cascade-connected inverters formed by devices 19, 20, 9 and 10 and is applied as a positive signal to the gates of devices 13 and 13D. The positive signal at the input passes through the pair of push-pull connected inverters 1, 2, 5 and 6 and is applied as a negative signal to the gate of device 14. The output node of the inverter 15 is connected to the gate of a totem-pole output circuit 25 formed by devices 17 and 18. The output node of the inverter 25 is the OCD output node connected to the output pad on the LSI chip. The problem addressed by the inverter 15 is how to compensate for charge loss at the node N, which is the output node for the inverter 15, which occurs when voltage noise at the output node OUT of the output inverter 25 is coupled at C through the capacitively coupled gate of the device 17 to node N. When negative-going voltage spikes appear at the output node OUT, those negative- going voltage spikes are capacitively coupled through C to the node N. This is overcome by arranging the relative size of the lo...