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Effective Utilization of a Two-Port Array

IP.com Disclosure Number: IPCOM000042639D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+4]

Abstract

One approach to system architecture relies on the premise that the most efficient architecture is one which is constrained to performing only 'single cycle' instructions. This implies that all loads and stores which allow register to register, storage to register, and register to storage operations can ideally be performed in one 'machine' cycle. The following abbreviations are used herein: (Image Omitted) A pipelined processor can be fashioned from such an architecture mold. Such pipelined processor may be provided with five banks of instruction control registers in the stream.

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Effective Utilization of a Two-Port Array

One approach to system architecture relies on the premise that the most efficient architecture is one which is constrained to performing only 'single cycle' instructions. This implies that all loads and stores which allow register to register, storage to register, and register to storage operations can ideally be performed in one 'machine' cycle. The following abbreviations are used herein:

(Image Omitted)

A pipelined processor can be fashioned from such an architecture mold. Such pipelined processor may be provided with five banks of instruction control registers in the stream. Within the formats of the architected instruction set, one can derive that the maximum number of register reads is three, as exemplified by instructions such as store instructions; similarly, the maximum number of register writes is two as in the case of an instruction such as 'update and load'. These are considered in an indexed EA format, which is the instruction format used when the contents of one register (RA) are added to the contents of a second register (RB) to form the main storage address that the contents of a third register (RS) will be stored. Within these limitations one could define a pipelined structure which executes up to three reads in the current instruction, and a maximum of two writes for a previous instruction in the same machine cycle. Seen in this light, a five-port General-Purpose Register (GPR) array would be required. Here, this same logical five-port is implemented using a physical two- port RAM (random-access memory) array. Description As illustrated in Fig. 1, all manipulation of information is done in high-speed registers internal to the processor. An array 1 of 32 x 32 GPRs can be addressed by byte, halfword or word. Fig. 1 also shows the associated latches and controls used to synchronize the input and output of the array on the processor chip. Each machine cycle consists of two (A and B) clock phases. All processor chips contain a series of control registers, each controlling a different phase of instruction execution, and the hardware registers which are used in that phase of execution. In general, the following actions are taken according to the machine cycle the instruction is in:

(Image Omitted)

The processing unit performs one of seven cycle types each machine cycle. The cycle types are performed in priority sequence: Returning to Fig. 1 we can now describe the GPR dataflow: *RA Output Register 2 - This register is in the GPR chip and is loaded from the GPR specified by the RA field or the RS field. It is controlled by the instruction in the read cycl...