Browse Prior Art Database

Bit Mapped Raster Display System

IP.com Disclosure Number: IPCOM000042674D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Eggerbrecht, EL: AUTHOR [+3]

Abstract

In a bit mapped raster display system, display data is stored in separate maps. Each map comprises eight modules storing the respective bits of each stored byte. The maps are updated either on a bit basis by selecting bit modules within the maps or on a byte basis by selecting a complete map. Three color maps MAP0 to MAP2, each comprising eight bit modules or planes, are addressed commonly from a CPU address bus 23. In a CRT refresh cycle, the maps are read together to output corresponding bytes to serializers 8, 9 and 10 which provide bit streams to address a color palette table 11. This table drives a color generator 12 to generate red, green and blue CRT drive signals. To update the color maps, gates 13, 14 and 15 are enabled to couple the maps to a CPU data bus 16.

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Bit Mapped Raster Display System

In a bit mapped raster display system, display data is stored in separate maps. Each map comprises eight modules storing the respective bits of each stored byte. The maps are updated either on a bit basis by selecting bit modules within the maps or on a byte basis by selecting a complete map. Three color maps MAP0 to MAP2, each comprising eight bit modules or planes, are addressed commonly from a CPU address bus 23. In a CRT refresh cycle, the maps are read together to output corresponding bytes to serializers 8, 9 and 10 which provide bit streams to address a color palette table 11. This table drives a color generator 12 to generate red, green and blue CRT drive signals. To update the color maps, gates 13, 14 and 15 are enabled to couple the maps to a CPU data bus 16. A map select register 17 and a bit module select register 18 determine the mode of writing into the maps. Two modes are employed. The first is a bit modification mode in which the map select register 17 contains all ones to select all the maps and the bit module select register 18 contains data to select a particular bit module in each map. Thus if register 18 stores a one bit in the module 0 locations, gate 19 is enabled to pass a 'write to memory' signal on line 22 to enable the 0 position bit modules of each map. Similarly, the 1-position bit modules are enabled through gate 20, and so on through to the 7-position bit modules through gate 21. The second mode is a...