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Multiprocessor-Cached DASD

IP.com Disclosure Number: IPCOM000042682D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Christian, JH: AUTHOR [+2]

Abstract

A caching DASD (direct-access storage device) peripheral data storage system employs a first processor, called a "main" processor, which handles all of the caching and data storage management functions. A second, or gap, processor, coupled to the main processor, provides data flow management for the peripheral data storage subsystem. This includes precisely managing certain buffering functions associated with gaps between data fields on a DASD, such that synchronous transfers between the DASD, the cache and the host processor are facilitated. One or more host processors are attached to the peripheral data storage system through a plurality of channel adapters.

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Multiprocessor-Cached DASD

A caching DASD (direct-access storage device) peripheral data storage system employs a first processor, called a "main" processor, which handles all of the caching and data storage management functions. A second, or gap, processor, coupled to the main processor, provides data flow management for the peripheral data storage subsystem. This includes precisely managing certain buffering functions associated with gaps between data fields on a DASD, such that synchronous transfers between the DASD, the cache and the host processor are facilitated. One or more host processors are attached to the peripheral data storage system through a plurality of channel adapters. Within the peripheral data storage system, a host-cache data flow couples the host processors to a cache, a host-DASD data flow couples the channel adapters through a modem and adapter to one or more disk files, termed "DASDs", while a third cache- DASD data flow couples the modem-adapters to the cache. A main processor coupled to all of the units, and which has a main control store, provides all of the management controls for the data storage system using known techniques. The host-DASD data flow may include a FIFO (first-in, first-out) buffer which enables synchronous transfers between a high-speed channel and an attached DASD. The gap processor manages the FIFO buffer and a gap-control store such that the later-described channel selection procedures are synchronized to the gap ...