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ALU Propagate and Generate Registers

IP.com Disclosure Number: IPCOM000042683D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR

Abstract

The speed of an Arithmetic Logic Unit (ALU) is increased by reducing the number of stages of delay in the design. The following expressions are used: A A clock for LSSD shift operation I Serial data input from adjacent LSSD latch C Clock CGA Clock Generate A (gates Bit X from A register) CGB Clock Generate B (gates Bit X from B register) CP Clock Propagate Gx Generate Register (Bit X) Px Propagate Register (Bit X) RAX Register A (Bit X) RBX Register B (Bit X) X Any bit (Bit X) of a 32-bit ALU word (B0-B31) Most processor designs feature two registers RAX and RBX that feed to an ALU. Here, the A and B registers are eliminated by modifying the propagate (P) and generate (G) selector gates in the ALU to form Px and Gx registers, respectfully.

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ALU Propagate and Generate Registers

The speed of an Arithmetic Logic Unit (ALU) is increased by reducing the number of stages of delay in the design. The following expressions are used: A A clock for LSSD shift operation I Serial data input from adjacent LSSD latch C Clock CGA Clock Generate A (gates Bit X from A register) CGB Clock Generate B (gates Bit X from B register) CP Clock Propagate Gx Generate Register (Bit X) Px Propagate Register (Bit X) RAX Register A (Bit X) RBX Register B (Bit X) X Any bit (Bit X) of a 32-bit ALU word (B0-B31) Most processor designs feature two registers RAX and RBX that feed to an ALU. Here, the A and B registers are eliminated by modifying the propagate (P) and generate (G) selector gates in the ALU to form Px and Gx registers, respectfully. The modification to the P and G selector gates required to form the individual P and G latches does not add additional delay stages to the ALU critical timing path. Therefore, the time required to transfer data through the A and B registers is totally eliminated and does not need to be considered in a critical path analysis. In addition to the increased performance, a hardware savings is also achieved. Logic for a typical ALU bit position using this approach is shown in the drawing.

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