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Main Storage Cycles Access With RAM Access Performance

IP.com Disclosure Number: IPCOM000042685D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Bhansali, MM: AUTHOR [+3]

Abstract

Cycling of main storage at approximately the access speeds of a random- access memory (RAM) allows a reduction in storage access time, improves processor performance, and increases the input/output (I/O) rate. This is done by interleaving storage RAM chips which allows accessing of a second storage location before the access cycle time required for a storage location has been completed. Interleaving storage addresses is a method of arranging storage locations so that their logical sequence is physically altered. All the even addresses are in one chip, and all the odd addresses are in the next. The least significant bit of a storage address determines which one of the two RAM chips will be accessed. RAM technologies specify an access time and a cycle time. Access time is the period for the data transfer to occur.

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Main Storage Cycles Access With RAM Access Performance

Cycling of main storage at approximately the access speeds of a random- access memory (RAM) allows a reduction in storage access time, improves processor performance, and increases the input/output (I/O) rate. This is done by interleaving storage RAM chips which allows accessing of a second storage location before the access cycle time required for a storage location has been completed. Interleaving storage addresses is a method of arranging storage locations so that their logical sequence is physically altered. All the even addresses are in one chip, and all the odd addresses are in the next. The least significant bit of a storage address determines which one of the two RAM chips will be accessed. RAM technologies specify an access time and a cycle time. Access time is the period for the data transfer to occur. The difference between cycle time and access time is dedicated for RAM chip recovery. This recovery time can be as great as 50% of the cycle time. Here, a second storage access starts to the chip that was not initially selected as soon as the specified access time for the first chip is satisfied without having to wait for the cycle time of the chip to be satisfied. This insures that the initial data transfer will be completed and a second transfer may be initiated, provided the access is not to the same chip. A logical flow chart is shown in the drawing. Most 'Instruction Fetch' routines and 'Cycle St...