Browse Prior Art Database

Central Control Unit Local Store Control

IP.com Disclosure Number: IPCOM000042696D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Pauporte, A: AUTHOR [+4]

Abstract

In a Central Control Unit, to address a random-access (RAM), memory local store from a very large number of possible sources, partial address source merging is performed to decrease the number of circuits and the time necessary to send the address to the RAM. The different types of address are generated in this way under read only storage ROS picocode control. Flexibility in address generation is therefore introduced by the picocode. Two ROS fields are used: the "Local Store Address Control", 4-bit field which specifies the source to be used to generate the local store address, and the "ROS Immediate" 7-bit field which provides a picocoded source of local store address. The different types of generated address are as follows: 1. General Register Addressing The instruction operation code, as shown on Fig.

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Central Control Unit Local Store Control

In a Central Control Unit, to address a random-access (RAM), memory local store from a very large number of possible sources, partial address source merging is performed to decrease the number of circuits and the time necessary to send the address to the RAM. The different types of address are generated in this way under read only storage ROS picocode control. Flexibility in address generation is therefore introduced by the picocode. Two ROS fields are used: the "Local Store Address Control", 4-bit field which specifies the source to be used to generate the local store address, and the "ROS Immediate" 7-bit field which provides a picocoded source of local store address. The different types of generated address are as follows: 1. General Register Addressing The instruction operation code, as shown on Fig. 1, includes an R1 3-bit field, an R1 ODD 2-bit field, and an R2 3-bit field. Any of these fields specifies a general register, one out of 8. In addition, each program level works with a dedicated group of general registers. The register group to be used is specified by an active program zone 3-bit indicator sent by the interrupt mechanism of the central unit for changing the current program level. The general register address is generated by concatenating the Rx fields and the Active program zone, as shown on Fig. 2. 2. External Register Addressing The operation code of the instructions dealing with the external registers includes an 7-bit E field. The E field of the Op- code either is used as such on the address bus or is ORed with the ROS immediate 7-bit field, as shown on Fig. 2. This allows an address different from the one shown in the E field to be generated when necessary. 3. General Register Addressing For "Exit" Ins...