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Address Compression for a Videotex Screen Buffer

IP.com Disclosure Number: IPCOM000042698D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Walker, MA: AUTHOR

Abstract

This article describes an algorithm and implementation circuitry for storing a screen buffer in a 1K (random-access memory) RAM when the screen buffer is defined as a 24-row by 40-column display. An example of its use can be seen in a videotex application.

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Address Compression for a Videotex Screen Buffer

This article describes an algorithm and implementation circuitry for storing a screen buffer in a 1K (random-access memory) RAM when the screen buffer is defined as a 24-row by 40-column display. An example of its use can be seen in a videotex application.

Commonly available commercial IC sets describe screen positions in terms of row and column address. The timing circuitry makes the row address available before the row address clock signal. Then the column address is incremented by the column clock. Normally such an application would use a 2K x 8 RAM plus gating circuitry. With algorithm and circuitry it is sufficient to use a 1K x 8 RAM. (Note: A 1K x 8 RAM can hold a screen size of 25 x 40.) Theory of Operation To understand the theory of operation, it is necessary to examine the row addresses for both the screen buffer and 1K RAM. Ten address lines are required to access a 1K RAM. These are shown in the table on the preceding page labelled 0 to 9), 9 being the most significant bit. A 5-bit row address is required for 24 rows. The table shows the memory address the row address and the difference between bits 5 to 9 and 0 to 4 of the memory and row addresses, respectively. Given the starting row address, the starting memory address made up by the following algorithm: Memory Address bits (0-2) = 0 Memory Address bit 3 = Bit 0 of the Row address Memory Address bit 4 = Bit 1 of the Row address Memory Address bits (5-9) =...