Browse Prior Art Database

Variable Standby Current Source Scheme

IP.com Disclosure Number: IPCOM000042704D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 59K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR [+4]

Abstract

This article describes a means to alter the standby current of a bipolar cell for: (1) stress testing (cell leakage characterization); and (2) multiple power level application. Bipolar memory cells such as CTS or Harper-PNP, are sensitive to leakages and device degradation due to their low current attribute. For arrays using these two cells, in order to improve reliability of the chip, a variable cell standby current scheme has been designed on chip to perform stress testing. The scheme provides a means to switch the cell's standby current from its normal value to one or two orders of magnitude lower. This power-down testing will stress the cells for low current leakage sensitivity. It will also simulate the effects of reduction in cell current caused by device degradation or tracking error. Design Description Fig.

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Variable Standby Current Source Scheme

This article describes a means to alter the standby current of a bipolar cell for:
(1) stress testing (cell leakage characterization); and (2) multiple power level application. Bipolar memory cells such as CTS or Harper-PNP, are sensitive to leakages and device degradation due to their low current attribute. For arrays using these two cells, in order to improve reliability of the chip, a variable cell standby current scheme has been designed on chip to perform stress testing. The scheme provides a means to switch the cell's standby current from its normal value to one or two orders of magnitude lower. This power-down testing will stress the cells for low current leakage sensitivity. It will also simulate the effects of reduction in cell current caused by device degradation or tracking error. Design Description Fig. 1 shows the circuitry of this variable current source scheme. The array for our illustration is assumed to be organized in 128 word lines by 80 cells. Each word line contains a normal standby current source formed from Ts and Rs. In addition to this current source, there is also a 128- way current mirror current source, each of the current mirrors being connected to a given word line, as shown. The total standby current applied to a word line is calculated as IWL = ISB + IVAR For each cell, it is given by ICELL = IWL/ of cells on a word line. The normal standby current source ISB is controlled by a reference generator CSGA (Fig. 2), which is switchable by input A. The variable current source IVAR is determined by the 128-way current mirror configuration, which is also switchable through input B. This variable current is given by IVAR = (IEE + ICC) / ( of WL + of Sense Tx) = (IEE + ICC / 132. ICC is a small constant current source defined by resistor RCC and a fixed voltage reference Vref . IEE is an adjustable current source defined by a voltage level applied at input B. IEE = VR2 / R2 = (VINB - VN - 2VBE) / R2 To monitor the switching of input B as well as to measure the applied word line current, a voltage sensing output is also provided on chip. Sensing transistors S1 to S4 and resistor ROUT serve this purpose. To further extend the range of the variable current source IVAR, an extra RCC resistor and T3 transistor are also provided on the 128-way current mirror configuration. These two devices can be connected in parallel, as indicated by the dotted lines in Fig. 1, by chip personality change. Modes of Operation (1) Normal current level - Input A is tied negative to turn on the reference generator CSGA, which enables the normal standby current source ISB . Input B is also tied negative to shut off IEE . In this mode, the wordline current is defined by IWL = ISB + IVAR = ISB + (ICC / 132) N ISB (1) When ISB...