Browse Prior Art Database

Bit Multiplex Driver

IP.com Disclosure Number: IPCOM000042720D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Jones, FD: AUTHOR [+2]

Abstract

When using a Shared Sense Amplifier Sensing Scheme, a driver is required to perform the array selection, optimize the signal sensing operation, and restore the sense amplifier. The circuit diagram illustrated in Fig. 1 performs this function in accordance with the waveform diagram of Fig. 2. Illustrated in Fig. 1 is a driver for bit multiplex left (ML1, ML2) and bit multiplex right (MR1, MR2). Transistors T5, T6, T7 and T8 perform the array selection. (The other multiplex lines are controlled by the corresponding transistors noted in prime notation). The up- level precharge signal (PR) precharges the driver internal node at the source of T5 (and T5') to VDD minus VT (where VDD is the supply voltage and VT is the threshold voltage of the field-effect transistors).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Bit Multiplex Driver

When using a Shared Sense Amplifier Sensing Scheme, a driver is required to perform the array selection, optimize the signal sensing operation, and restore the sense amplifier. The circuit diagram illustrated in Fig. 1 performs this function in accordance with the waveform diagram of Fig. 2. Illustrated in Fig. 1 is a driver for bit multiplex left (ML1, ML2) and bit multiplex right (MR1, MR2). Transistors T5, T6, T7 and T8 perform the array selection. (The other multiplex lines are controlled by the corresponding transistors noted in prime notation). The up- level precharge signal (PR) precharges the driver internal node at the source of T5 (and T5') to VDD minus VT (where VDD is the supply voltage and VT is the threshold voltage of the field-effect transistors). The trapped charge at the gate of T9 (and T9') holds the multiplex line voltages at VDD. The word address (W6) signal at the gate of T6 (and T6') determines whether the left or right side array is to be selected. The word address (W7) signal at the gate of T7 (and T7') determines whether the top or bottom of the chip is to be selected. In the present example, W6 and W7 are actively held down, the voltage on the unselected multiplex lines (MR1, ML2, MR2) is discharged through the transfer gate T3'. The Sense Latch Set Slow (SLS) clock pulse at the gate of T8 (and T8') turns on T8 to slowly discharge the selected multiplex line through transistor T3. The optimum sense amplifier operati...