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Browse Prior Art Database

Bit Cell for a Five-Port RAM

IP.com Disclosure Number: IPCOM000042723D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 139K

Publishing Venue

IBM

Related People

Culican, EF: AUTHOR [+3]

Abstract

Disclosed is a random-access memory (RAM) capable of two writes and three reads in one RAM cycle. The RAM is DC testable, has a quick fabrication turn around time, and requires no special product assurance qualification. The bit cell for this five-port macro utilizes seven AND-INVERT (AI) blocks interconnected as shown in Fig. 1. AI blocks 1 through 4 make up the latch ports and blocks 5 through 7 are the 3 output ports. When the Read select R1, R2 and R3 are down, the outputs are unselected. Either Data Output 1, 2 or 3 or any combination of the outputs may be selected in one bit, but for any one output port only one word can be selected. The system permits only one set of data to be written at a given time. When the clock signal W1 or W2 is up, the corresponding data is written into the latch.

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Bit Cell for a Five-Port RAM

Disclosed is a random-access memory (RAM) capable of two writes and three reads in one RAM cycle. The RAM is DC testable, has a quick fabrication turn around time, and requires no special product assurance qualification. The bit cell for this five-port macro utilizes seven AND-INVERT (AI) blocks interconnected as shown in Fig. 1. AI blocks 1 through 4 make up the latch ports and blocks 5 through 7 are the 3 output ports. When the Read select R1, R2 and R3 are down, the outputs are unselected. Either Data Output 1, 2 or 3 or any combination of the outputs may be selected in one bit, but for any one output port only one word can be selected. The system permits only one set of data to be written at a given time. When the clock signal W1 or W2 is up, the corresponding data is written into the latch. When the clock signal W1 or W2 goes up, the data is latched. The seven AI design may be implemented from six internal cells in a 2 x 3 rectangular block. The seventh AI may be implemented from devices in an area normally used for global wiring channels. Fig. 2 depicts the arrangement of the seven AIs. Fig. 3 schematically depicts the book metal for the seven circuits and the book metal for the one- bit macro. Fig. 4 illustrates the efficient utilization of first level horizontal wiring channels in the fabrication of the bit cell.

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