Browse Prior Art Database

CCU Data Flow Controlled by Mixed Picocode/Hardware

IP.com Disclosure Number: IPCOM000042724D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Lechaczynski, M: AUTHOR [+4]

Abstract

To maintain the high performance level of a central control unit (CCU) controlled by control words in a read-only storage (ROS), a hardware control is available either to generate controls independently from the ROS for the first machine control word or to modify the ROS output word. Thanks to the hardware, the cycle time duration as well as the number of cycles necessary to perform the operation are decreased. The machine control word necessary for the first cycle of most of the instructions, i.e., A and B operand bus source gating, is generated without adding one CCU cycle. The general control logic flow is shown in Fig. 1. The register POP contains the instruction. Based on its decode, a ROS first address is generated and the ROS word is immediately latched in a "ROS output word" register.

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CCU Data Flow Controlled by Mixed Picocode/Hardware

To maintain the high performance level of a central control unit (CCU) controlled by control words in a read-only storage (ROS), a hardware control is available either to generate controls independently from the ROS for the first machine control word or to modify the ROS output word. Thanks to the hardware, the cycle time duration as well as the number of cycles necessary to perform the operation are decreased. The machine control word necessary for the first cycle of most of the instructions, i.e., A and B operand bus source gating, is generated without adding one CCU cycle. The general control logic flow is shown in Fig. 1. The register POP contains the instruction. Based on its decode, a ROS first address is generated and the ROS word is immediately latched in a "ROS output word" register. The "ROS output word" register cannot control directly the A bus gating and the B bus gating of the CCU data flow which uses bit slicing with 3 bits per chip of the CCU. With a CCU comprised of 9 chips, the 9 chips must receive the A/B bus gating control which is not allowed by the ROS fan-out. A "machine control word" register, located in the data flow chips, is used. One CCU cycle is necessary for the signals to go from one register to another, therefore, two cycles would be necessary with a ROS only control to set up the A/B bus gating control (1 cycle POP T "ROS output word" register, 1 cycle "ROS output word" register T "machine control word" register). Hardware control logic allows one cycle to be saved by generating directly the "machine control word" from the POP decode as far as the "A/B bus gating control" is concerned. The logic control flow, shown on Fig. 2, relates to the ROS output word modification. It is the same as the one shown on Fig. 1 with the following exception: the "machine control word" is not latched in this case. It is the ou...