Browse Prior Art Database

Second Level Cache for MP Systems

IP.com Disclosure Number: IPCOM000042727D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

The figure shows a computing machine with a second-level cache of 500 to 2000K bytes inserted between the first level cache and the SCU (Storage Control Unit)/memories. Properties of Second Level Cache A. CPU access time of 3 to 10 CPU cycles - from Decode-ADR Generate. The transfer of data between the first and second level cache will be done, if possible, on a first level cache line size on a parallel basis; i.e., if first level cache has a 64-byte line, then form factors of both first and second level cache chips are such that 64 bytes of data can be read or written from each cache in their respective cycle times; and associativity is handled within this attribute of the cache. B. 512-byte line - or whatever byte line size is chosen as most efficient - it should have at least as many lines as the first level cache. C.

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Second Level Cache for MP Systems

The figure shows a computing machine with a second-level cache of 500 to 2000K bytes inserted between the first level cache and the SCU (Storage Control Unit)/memories. Properties of Second Level Cache A. CPU access time of 3 to 10 CPU cycles - from Decode-ADR Generate. The transfer of data between the first and second level cache will be done, if possible, on a first level cache line size on a parallel basis; i.e., if first level cache has a 64-byte line, then form factors of both first and second level cache chips are such that 64 bytes of data can be read or written from each cache in their respective cycle times; and associativity is handled within this attribute of the cache. B. 512-byte line - or whatever byte line size is chosen as most efficient - it should have at least as many lines as the first level cache. C. 4-way set associativity - or whatever associativity the first level cache has. D. At least 8 times the size of first level cache. E. Store-through as against store-in-cache algorithm for first level cache. Any data that is written to memories updates these caches. F. These second level caches are always maintained as a direct image of the data in memory, and the directories are absolute. G. All data that is written into memory from any CPU or EXDC (channel) is passed from SCU to the controls of all second level caches and they update their contents, if required, simultaneously and asynchronously.
H. The controls may contain two directories, one for continuous interrogation for requests from the CPU and the second to handle data from other CPUs/EXDCs that are being written into memory. I. A dedicated second level cache is shown with each CPU in the figure, but this computing system is not limited to dedicated second level caches, i.e., two or more CPUs could share a second level cache. (Greater associativity would be required for simplicity.) J. In all cases the SCU handles first level caches. K. The Protect Directories of the second level caches will contain an exclusive field for each first level cache line number of bytes. For example, if the first level cache line contained 64 bytes, then the second level cache directory would contain an exclusive field for each 64 bytes contained in the second level cache. The function of the exclusive field is to indicate that any first level cache has exclusive control of this 64 bytes, and that this data will be unavailable until the first level ca...