Browse Prior Art Database

Cross-Interrogate Line Buffers

IP.com Disclosure Number: IPCOM000042742D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Rechtschaffen, RN: AUTHOR [+2]

Abstract

A major source of multiprocessor degradation is the cross-interrogation of one processor's cache by the other. The following reduces the penalty for a cross-interrogation. Analysis has shown that a technique based on the least recently used (LRU) status of cache lines subject to cross-interrogation identifies these lines as the subject of re-cross-interrogation by the original processor. The penalty experienced by a processor whose line is cross-interrogated can be reduced if the line can merely be invalidated and a current copy is provided by the proposed cross-interrogate (XI) line buffer. Fig. 1 shows a 2-way multiprocessor (MP) which maintains XI buffers for a subset of cache lines.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Cross-Interrogate Line Buffers

A major source of multiprocessor degradation is the cross-interrogation of one processor's cache by the other. The following reduces the penalty for a cross- interrogation. Analysis has shown that a technique based on the least recently used (LRU) status of cache lines subject to cross-interrogation identifies these lines as the subject of re-cross-interrogation by the original processor. The penalty experienced by a processor whose line is cross-interrogated can be reduced if the line can merely be invalidated and a current copy is provided by the proposed cross-interrogate (XI) line buffer. Fig. 1 shows a 2-way multiprocessor (MP) which maintains XI buffers for a subset of cache lines. Each of these lines was identified by being itself the subject of a cross-interrogation and having the proper LRU status at the time of cross-interrogation. The cache penalty on the interrogated processor can be reduced by as many cycles as it takes to transfer a line into or out of its cache. A special bit for each line is set in the cache directory to signal the processor to store in both the cache and the XI buffer simultaneously, thereby assuring that the XI buffer contains a current copy of the line. The State Diagram (Fig. 2) shows actions on successive cross- interrogations of the same line.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]