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Variable Frequency Oscillator Using a Frequency Discriminator

IP.com Disclosure Number: IPCOM000042753D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Rae, JW: AUTHOR [+2]

Abstract

To increase the capture range of variable frequency oscillators used in hard disk files, a frequency discriminator is operated in parallel with the usual phase discriminator during the fast synchronization mode. Conventionally, the variable frequency oscillator includes voltage-controlled oscillator (VCO) 1 generating a 2F clock signal. VCO 1 is part of a phase-locked loop which keeps the clock signal in phase with the data signal read back from the disk. The phase-locked loop includes phase discriminator 2 which controls charge pump 3. The latter creates, as needed a burst of charge into loop filter 4 so that the clock frequency generated by VCO 1 is adjusted after appropriate buffering in buffer 5.

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Variable Frequency Oscillator Using a Frequency Discriminator

To increase the capture range of variable frequency oscillators used in hard disk files, a frequency discriminator is operated in parallel with the usual phase discriminator during the fast synchronization mode. Conventionally, the variable frequency oscillator includes voltage-controlled oscillator (VCO) 1 generating a 2F clock signal. VCO 1 is part of a phase-locked loop which keeps the clock signal in phase with the data signal read back from the disk. The phase-locked loop includes phase discriminator 2 which controls charge pump 3. The latter creates, as needed a burst of charge into loop filter 4 so that the clock frequency generated by VCO 1 is adjusted after appropriate buffering in buffer 5. Frequency discriminator 6 is mounted in parallel with phase discriminator 2 and is active only during the fast synchronization mode when the data being read from the disk is the synchronization field and the bit pattern is known to correspond to one pulse for a given number of clock cycles. Frequency discriminator 6 contains up- down counter 7 whose count is incremented by one for each clock cycle that is expected to coincide with a readback data pulse (UP input from VCO 1, through divider-by-two 8) and is decremented by one as each readback data pulse arrives (DOWN input from readback data input). Counter 7 is enabled only during fast synchronization mode. If the count ever becomes greater than + 1 or less than - 1, a frequency difference is indicated. A count of + 2 indicates that the clock frequency is higher than the data frequency and a pulse is generated to set latch 9. Similarly, a count of - 2 indicates that the clock frequency is lower than the data frequency and a pulse is generated to set latch 10. Both latches 9 and 10 are reset by single-shot circuit 11 which lengthens the output pulses of counter 7 through OR circuit 12. The output pulse of single-shot 11 also resets counter 7 a...