Browse Prior Art Database

Dual Storage System

IP.com Disclosure Number: IPCOM000042755D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Capowski, RS: AUTHOR

Abstract

In contemporary large computer system design there is a trend to use a portion of main storage (MS) as residence for crucial control information. The occurrence, therefore, of a MS uncorrectable error while accessing this control data can cause abrupt disruption of system operation with severe consequences to on-line processing. As a means to significantly reduce the probability of such processing disruptions, redundant copies of critical data can be stored in separate MS locations. The described mechanism provides a method of selecting an alternate MS address in a storage system where dual copies of specified data are stored in secondary, as well as primary, MS locations.

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Dual Storage System

In contemporary large computer system design there is a trend to use a portion of main storage (MS) as residence for crucial control information. The occurrence, therefore, of a MS uncorrectable error while accessing this control data can cause abrupt disruption of system operation with severe consequences to on-line processing. As a means to significantly reduce the probability of such processing disruptions, redundant copies of critical data can be stored in separate MS locations. The described mechanism provides a method of selecting an alternate MS address in a storage system where dual copies of specified data are stored in secondary, as well as primary, MS locations. The primary address is provided conventionally by the requestor; and also a special access tag is provided to specify when data is to be stored additionally at a secondary address. Depending on the storage system (interleaving, bus structure, etc.), the stores can be performed in parallel or sequentially. In either case, the address of the secondary store is generated either by accessing an address translation array or by concatenating a portion of the supplied primary address to the contents of a modifiable base address register in the memory controller. Fetch accesses are to the requestor supplied (primary) address. When those requests are accompanied by the special access tag, and good useable data cannot be obtained from the primary address (i.e. uncorrectable error is d...