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Automatic RAM Repair of Single-Bit Hard Errors Using Spare Bits

IP.com Disclosure Number: IPCOM000042758D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Blanchard, RC: AUTHOR [+2]

Abstract

Often, when a memory is organized by bytes 8 or 9 bits in width, there are spare bits available. These can be used to substitute for failed RAM (random-access memory) bits. The figure shows an overall diagram of an error correction code (ECC) and error repair logic design, although either could be used without the other, if desired. The elements that have been added to the normal ECC design are the repair mask register, gating logic or the RAM interface, the status register and some control logic. The operation is as follows. At power-on time, the RAM is loaded with specific data test patterns to determine if any hard error failures have occurred. If a single-bit hard error is found, the bit in the repair mask register corresponding to the failed bit is set.

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Automatic RAM Repair of Single-Bit Hard Errors Using Spare Bits

Often, when a memory is organized by bytes 8 or 9 bits in width, there are spare bits available. These can be used to substitute for failed RAM (random- access memory) bits. The figure shows an overall diagram of an error correction code (ECC) and error repair logic design, although either could be used without the other, if desired. The elements that have been added to the normal ECC design are the repair mask register, gating logic or the RAM interface, the status register and some control logic. The operation is as follows. At power-on time, the RAM is loaded with specific data test patterns to determine if any hard error failures have occurred. If a single-bit hard error is found, the bit in the repair mask register corresponding to the failed bit is set. This automatically switches the use of the failing RAM bit to a spare RAM bit, which is then tested to verify that all bits are now working correctly. If sufficient logic circuitry is available, any data bit could be switched to any spare bit. If another single-bit error (hard or soft) occurs during this session, the ECC logic will handle it and prevent user interruption. At power-on of the following session, additional hard error failures (if they are in different groups) will be repaired. The ECC handles soft errors and hard errors if they occur during a session, and the repair logic repairs hard error failures at the start of each session. Th...