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Microcode Repackaging Technique

IP.com Disclosure Number: IPCOM000042759D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Cain, RG: AUTHOR [+2]

Abstract

This article provides a means for repackaging either programs or microcode in a way which reduces the number of misses in a pageable control store or cache containing a program. A program or microcode is packaged so as to reduce the number of fetches of control store lines in order to improve computer performance. The fundamental idea is the creation and use of a transition frequency matrix (TFM). The TFM represents the frequency of stepping from any branch instruction (i.e., from word) to any target instruction (i.e., to word). Programs (or microprograms) involve a good deal of branching. Some programs may consist of unique code, and other programs may share code.

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Microcode Repackaging Technique

This article provides a means for repackaging either programs or microcode in a way which reduces the number of misses in a pageable control store or cache containing a program. A program or microcode is packaged so as to reduce the number of fetches of control store lines in order to improve computer performance. The fundamental idea is the creation and use of a transition frequency matrix (TFM). The TFM represents the frequency of stepping from any branch instruction (i.e., from word) to any target instruction (i.e., to word). Programs (or microprograms) involve a good deal of branching. Some programs may consist of unique code, and other programs may share code. The TFM reveals the most frequently traversed paths, and repackaging can optimize them by putting both branch and target instructions into the same line in a cache or control store. For example, each line in a cache or control store may contain 32 words. A high usage program segment of up to one line in length may inadvertently be packaged such that branch and target instructions (microinstructions) span a line boundary. Repackaging may move that instruction pair to reside entirely within a single line, resulting in one fetch instead of two from main storage. In this manner, the repackaging reorders the instruction (or microinstruction) words in a way which contains the working set in fewer fetched lines and thereby reduces the frequency of cache or control store misses. The repackaging can be done at any time in the life of a product. The basic principle reorders portions of a program by mapping the high usage paths into fewer cache lines in order to reduce the number of cache misses and thereby improve computer performance. The processor is made to run a workload while the pair of addresses comprising a branch instruction (or microinstruction) and its target instruction (or microinstruction) is recorded by either a builtin or externally attached hardware monito...