Browse Prior Art Database

Block Graphics Generator

IP.com Disclosure Number: IPCOM000042764D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Eggebrecht, LC: AUTHOR [+2]

Abstract

In certain computer systems, it is desirable to have the option of providing block graphic characters by using either a hardware generator or character codes included in the conventional character generator read-only storage (ROS). For instance, the Intel 8275 CRT controller includes two outputs called LA0 and LA1 which with other logic generate the block graphic character signals. However, when connected in a conventional manner, the hardware-generated block graphic characters do not permit continuous horizontal lines, since only 8 dots are provided in a 9 dot space. Referring to the figure, the system data bus is connected to the CRT controller 10 and causes address signals to be provided from the address bus to a character generator 12.

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Block Graphics Generator

In certain computer systems, it is desirable to have the option of providing block graphic characters by using either a hardware generator or character codes included in the conventional character generator read-only storage (ROS). For instance, the Intel 8275 CRT controller includes two outputs called LA0 and LA1 which with other logic generate the block graphic character signals. However, when connected in a conventional manner, the hardware-generated block graphic characters do not permit continuous horizontal lines, since only 8 dots are provided in a 9 dot space. Referring to the figure, the system data bus is connected to the CRT controller 10 and causes address signals to be provided from the address bus to a character generator 12. If character generator 12 includes block graphic characters, they may be addressed through the address bus mechanism. The output of character generator 12 is applied to the A set of 8 inputs of multiplexer 14, which can be selected by a logic "O" signal applied to the select (S) input thereof to provide the data at the output of the multiplexer 14. This data is, in turn, applied to shift register (S/R) 16, which converts the parallel input data applied thereto to a serial output video signal to be displayed on a raster scan CRT display device. If it is desirable to use the hardware block graphic character feature of the CRT controller 10, then the LA0 and LA1 lines are applied to the A and B inputs of a...