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Dynamic Shared Reference Voltage Cell

IP.com Disclosure Number: IPCOM000042773D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 96K

Publishing Venue

IBM

Related People

Grynberg, R: AUTHOR [+4]

Abstract

The sense amplifier reference cell in Figs. 1 and 2 provides a tracking reference voltage for a dynamic RAM while minimizing area and noise. The reference cell has the following features: 1) Shared bit line pairs 2) Bit lines produce the reference voltage by using the mean difference between "1" and "0" levels 3) Identical to and tracks with storage cells a) Process Bias b) Leakage c) Plate Voltage 4) Balanced load during sense amplifier setting 5) Balanced reference word line noise coupling The half voltage shared reference cell (see layout) consists of two regular cells S1 and S2 connected back to back. S1 provides a reference on BL1 or BL2 for cells on bit lines BL1 or BL2, and S2 provides a reference on BL1 or BL2 for cells on bit lines BL1 or BL2. The bit line pairs are selected by multiplex device pairs 3, 4 and 5, 6.

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Dynamic Shared Reference Voltage Cell

The sense amplifier reference cell in Figs. 1 and 2 provides a tracking reference voltage for a dynamic RAM while minimizing area and noise. The reference cell has the following features: 1) Shared bit line pairs 2) Bit lines produce the reference voltage by using the mean difference between "1" and "0" levels 3) Identical to and tracks with storage cells a) Process Bias b) Leakage c) Plate Voltage 4) Balanced load during sense amplifier setting 5) Balanced reference word line noise coupling The half voltage shared reference cell (see layout) consists of two regular cells S1 and S2 connected back to back. S1 provides a reference on BL1 or BL2 for cells on bit lines BL1 or BL2, and S2 provides a reference on BL1 or BL2 for cells on bit lines BL1 or BL2. The bit line pairs are selected by multiplex device pairs 3, 4 and 5, 6. The two storage pockets S1 and S2 are preset at "1" and "0" from their respective bit lines when the reference cell word lines WDML and WDMR are both brought high. Both reference cell word lines are returned to ground at the end of the selected cycle, closing the transfer gates 7 and 8. The 0/EQD line is then brought high, equalizing the signal in the storage pockets S1 and S2. 0/EQD is returned to ground at the beginning of the selected cycle. The word line of the selected reference cell is brought high, transferring the cell's half charge onto its bit line. The selected and unselected reference cell word...