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CMOS Twin-Tub ROX Structure With Self-Aligned Field Implants

IP.com Disclosure Number: IPCOM000042787D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Terman, LM: AUTHOR

Abstract

This article describes a processing sequence for obtaining a CMOS twin- tub structure in which the field implants in each of the wells is self- aligned to the well edge and the device areas. The process sequence is as follows: 1. Deposit an N- epitaxial layer on an N+ silicon wafer. (A non- epi substrate may be used and is shown for simplicity in the figures.) 2. Grow a thin layer of silicon dioxide on the N- epitaxial layer. 3. Deposit a thin layer of silicon nitride on the silicon dioxide layer. 4. Deposit, by chemical vapor deposition, a layer of polycrystalline silicon on the silicon nitride layer. 5. Apply photoresist (PR), expose and define device areas for both N and P-channel devices.

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CMOS Twin-Tub ROX Structure With Self-Aligned Field Implants

This article describes a processing sequence for obtaining a CMOS twin- tub structure in which the field implants in each of the wells is self- aligned to the well edge and the device areas. The process sequence is as follows: 1. Deposit an N- epitaxial layer on an N+ silicon wafer. (A non- epi substrate may be used and is shown for simplicity in the figures.) 2. Grow a thin layer of silicon dioxide on the N- epitaxial layer. 3. Deposit a thin layer of silicon nitride on the silicon dioxide layer. 4. Deposit, by chemical vapor deposition, a layer of polycrystalline silicon on the silicon nitride layer. 5. Apply photoresist (PR), expose and define device areas for both N and P-channel devices. Photoresist-polysilicon-Si3N4 stacks remain over device areas while SiO2 remains on the surface of the N- epitaxial layer, as shown in Fig. 1. 6. Strip the remaining photoresist shown in Fig. 1, and apply and define a new photoresist mask, as shown in Fig. 2, for the purpose of forming an N-well. 7. Ion implant N-well field doping using a low voltage implant, as shown in Fig. 3. 8. Etch the polysilicon from the stacks exposed in Step 6 in the N-well areas and ion implant the N-well using a high voltage implant, as shown in Fig. 3. 9. Deposit aluminum over the entire wafer. Lift-off resist and aluminum, producing the structure shown in Fig. 3. 10. Ion implant P-well field doping using low voltage implant. 11. Etch o...