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# Fixed-Bias and Variable-Bias Random Pattern Generator

IP.com Disclosure Number: IPCOM000042807D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 29K

IBM

## Related People

Hermann, AL: AUTHOR

## Abstract

With the increased amount of testing using randomly generated patterns, there will be circuits where biased random patterns are more efficient than patterns containing an equal distribution of 1's and 0's. Using the circuit illustrated in Fig. 1, a random pattern can be generated with a biased distribution of 1's and 0's. To accomplish this, a number of bits are selected from a random pattern generator, such as a Linear Feedback Shift Register (LFSR), the bits being either ANDed or ORed together depending on whether the pattern is to be biased toward 0 or 1. Table 1 illustrates the biasing for n=2 through 6: Alternatively, referring to Fig. 2, the 'n' number of bits (A) selected from the random pattern generator are compared with n bits (B) from the bias control.

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Fixed-Bias and Variable-Bias Random Pattern Generator

With the increased amount of testing using randomly generated patterns, there will be circuits where biased random patterns are more efficient than patterns containing an equal distribution of 1's and 0's. Using the circuit illustrated in Fig. 1, a random pattern can be generated with a biased distribution of 1's and 0's. To accomplish this, a number of bits are selected from a random pattern generator, such as a Linear Feedback Shift Register (LFSR), the bits being either ANDed or ORed together depending on whether the pattern is to be biased toward 0 or 1. Table 1 illustrates the biasing for n=2 through 6: Alternatively, referring to Fig. 2, the 'n' number of bits (A) selected from the random pattern generator are compared with n bits (B) from the bias control. If A is greater than or equal to B, the output of the comparator is set to 1. As illustrated in Table II, for n=2, 3 and 4, the percentage of 1's generated can be controlled by the value in the bias control and the number of bits compared (n). If pattern sets containing all 1's and also all 0's are required, they can be generated by exclusive ORing the output of the comparator (R) with a complement control line C. To generate all 1's, B is set to all 0's and C is set to 0. To generate all 0's, B is set to all 0's and C is set to 1.

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