Browse Prior Art Database

Loading and Sensing Internal Processor Registers From Input/Output Devices

IP.com Disclosure Number: IPCOM000042811D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Batalden, GD: AUTHOR [+4]

Abstract

Central processing unit (CPU) 1 has two processors: Main storage processor (MSP) 2 which executes assembler-level system-support programs and user code located in main storage 3, and control storage processor (CSP) 4 which executes system-control programs and I/O-control microcode located in control storage 5, and which transfers data through channel logic 7 to and from system channel 9. MSP 2 contains registers 8 necessary for executing the assembler-level code, for providing status, and for addressing main storage (address translation registers (ATRs)). The CSP contains a group of cycle steal address registers (CSARs) 6 which are selected by cycle-stealing I/O attachments via channel 9. The CSARs are then subsequently used to address control storage, main storage, or MSP registers during cycle-steal operations.

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Loading and Sensing Internal Processor Registers From Input/Output Devices

Central processing unit (CPU) 1 has two processors: Main storage processor (MSP) 2 which executes assembler-level system-support programs and user code located in main storage 3, and control storage processor (CSP) 4 which executes system-control programs and I/O-control microcode located in control storage 5, and which transfers data through channel logic 7 to and from system channel 9. MSP 2 contains registers 8 necessary for executing the assembler- level code, for providing status, and for addressing main storage (address translation registers (ATRs)). The CSP contains a group of cycle steal address registers (CSARs) 6 which are selected by cycle-stealing I/O attachments via channel 9. The CSARs are then subsequently used to address control storage, main storage, or MSP registers during cycle-steal operations. The system supports two conventional modes of cycle steal, burst mode and base cycle-steal mode, for accessing main storage or control storage. Prior to performing a cycle- steal operation to/from control storage or main storage, it is first necessary to load, via microcode, the appropriate CSARs 6 in the CSP register stack, and the appropriate MSP registers 8, such as the control mode register and ATRs. It is also necessary to provide the appropriate microcoded interlocks to lock out other devices in cases where multiple devices share CPU resources, such as ATRs and CSARs. This set-up overhead normally requires a great deal of time. Much of this overhead time can be eliminated by providing the capability to sense and/or load CSARs 6 and MSP registers 8 from the I/O attachments 10-12 directly during the cycle-steal operation prior to the actual data transfer. This capability eliminates the need for mi...