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Use of Storage Address Register for Storage Protection

IP.com Disclosure Number: IPCOM000042837D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Saurel, A: AUTHOR [+2]

Abstract

This article relates to the implementation of a storage protection mechanism in a central unit with a minimum number of registers and circuits. The same register and associated hardware are used to perform the key setting and the key value comparison and checking. Various storage keys assigned to each of the main storage segments are necessary to perform the storage protect function. The following implementation of the storage protect mechanism allows the logic circuit number to be minimized by using the storage address register (SAR) for counting the various storage keys in a key random-access memory. The storage protect is a means for notifying the control program whenever the contents of the storage are accessed for an unauthorized modification or unauthorized code execution.

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Use of Storage Address Register for Storage Protection

This article relates to the implementation of a storage protection mechanism in a central unit with a minimum number of registers and circuits. The same register and associated hardware are used to perform the key setting and the key value comparison and checking. Various storage keys assigned to each of the main storage segments are necessary to perform the storage protect function. The following implementation of the storage protect mechanism allows the logic circuit number to be minimized by using the storage address register (SAR) for counting the various storage keys in a key random-access memory. The storage protect is a means for notifying the control program whenever the contents of the storage are accessed for an unauthorized modification or unauthorized code execution. Setting the keys is performed by the control program of the central control unit using a set key output instruction which causes the contents of a general register (R) to be used to address and/or set the storage and protect keys. The attempts to modify the storage contents and to execute instructions are monitored by: - storage protect based on read-only key - storage protect on storage key and user key. These mechanisms must be enabled by software using the following output set key (SK) instruction: Output set key instruction

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To enable the mechanism, a set key instruction with a bit 1 equal to 1 in byte 1 must be performed. Output "set key" instructions are also used to set all the keys as follows: - bit 4 in byte 0 to bit 2 in byte X specify the SKA (this is the address of the storage block associated with the storage key or with the read-only key). - bits 7 to 3 in byte 0 specify the UKA. - bit 1 in byte 1 enables the mechanism. - bits 2 and 3 in byte 1 specify the key type. - bit 4 in byte 1 specifies whether the key value has to be modified or not. - bits 5 to 7 in byte 1 specify the 3-bit key value. The key setting is allowed to users having a 000 user key only. If a user executing in a non-zero key executes an output set key instruction, the keys are not changed. The input set key instruction is used to insert the read only, storage or user key addressed by the last output key instruction set into byte 1, bits 5-7 of the register specified. The two basic modes of operation are: 1 - key loading 2 - storage protect checking In both modes, the information comes from the SAR which contains either the bits of the register specified as the external register by the output "set key" instruction for key loading or the storage address for storage protection checking. The same bits of the SAR are used to address the 2K-byte segment of the main storage when performing any storage operation like load/ store instruction, instruction prefetch, etc. Fi...