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Interrupt Request Circuit

IP.com Disclosure Number: IPCOM000042842D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Russell, RE: AUTHOR [+2]

Abstract

This article describes interrupt request circuitry for handling multiple interrupt requests to a processor where a separate microprocessor is used to control the interrupt function. In Fig. 1, the block diagram shows the use of the interrupt circuit. For clarity, the diagram does not show such items as address/ data bus arbitration and address decode logic which would normally be incorporated in two-processor systems. Two different interrupt request circuits are shown in Figs. 1 and 2. They are designed to selectively post and clear four levels of interrupts when the computer acknowledges the interrupt. The four levels of interrupts are as follows: 1. Posting an interrupt - A device that wishes to post an interrupt activates the data lines, address lines and write lines, as shown in Fig. 1. In Figs.

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Interrupt Request Circuit

This article describes interrupt request circuitry for handling multiple interrupt requests to a processor where a separate microprocessor is used to control the interrupt function. In Fig. 1, the block diagram shows the use of the interrupt circuit. For clarity, the diagram does not show such items as address/ data bus arbitration and address decode logic which would normally be incorporated in two-processor systems. Two different interrupt request circuits are shown in Figs. 1 and 2. They are designed to selectively post and clear four levels of interrupts when the computer acknowledges the interrupt. The four levels of interrupts are as follows: 1. Posting an interrupt - A device that wishes to post an interrupt activates the data lines, address lines and write lines, as shown in Fig.
1. In Figs. 2 and 3, circuit lines A0 and A1 must have the binary-encoded value of the interrupt. When the write and data lines are conditioned, the interrupt level desired is posted. 2. Clearing an interrupt - The method of clearing an interrupt is similar to the posting of an interrupt, except the logic values (voltage levels) of the data lines are changed. The specified interrupt is now cleared. 3. Automatic clearing of an interrupt - After conditioning the A0 and A1 address lines, the processor acknowledges the interrupt by using the ACK line. The data line, DATA0 is not driven by the processor. This allows resistor R to condition DATA0 to the inacti...