Browse Prior Art Database

Programmable Vector Mask Register Bits Selection and Control

IP.com Disclosure Number: IPCOM000042855D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Ngai, CH: AUTHOR [+3]

Abstract

The object of this disclosure is to minimize hardware by sharing existing hardware. This disclosure describes a better way to load and read a Vector Mask Register (VMR) by using the existing hardware, which is system programmable, thereby providing the use of identical hardware. In a Vector Processor, Vector Mask (VM) bits are required to be read from, or loaded into, the VMR. If the Vector Processor is a serial processor (processing one element at a time), this would not be a problem because the processor probably contains the entire VMR. However, if the Vector Processor is a parallel design processor, which contains many element processors, the reading and loading of the VM bits could be a problem because the VM bits are distributed among the element processors.

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Programmable Vector Mask Register Bits Selection and Control

The object of this disclosure is to minimize hardware by sharing existing hardware. This disclosure describes a better way to load and read a Vector Mask Register (VMR) by using the existing hardware, which is system programmable, thereby providing the use of identical hardware. In a Vector Processor, Vector Mask (VM) bits are required to be read from, or loaded into, the VMR. If the Vector Processor is a serial processor (processing one element at a time), this would not be a problem because the processor probably contains the entire VMR. However, if the Vector Processor is a parallel design processor, which contains many element processors, the reading and loading of the VM bits could be a problem because the VM bits are distributed among the element processors. For the sake of illustration, assume there are 16 element processors each containing 4 elements to configure a 64-element Vector Processor. Each element processor will have 4 VM bits, one per element. One way to load the VMR is to deal with one element processor at a time. This is time consuming because there are many element processors. However, another way to load the VMR is from the data bus. The data bus is connected to the element processors as shown in Fig. 1. Each element processor must select its corresponding 4 VM bits from the 64 VM bits on the data bus. Since the element processors are identical, some kind of selection mechanism is needed to personalize each eleme...