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Multiplexed Address on a Translating Storage Controller to Conserve Pins

IP.com Disclosure Number: IPCOM000042873D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Hester, PD: AUTHOR [+2]

Abstract

Certain storage channel controllers have a limitation on the number of available pins.The method described in this article utilizes time multiplexing to conserve pins without adversely affecting performance. In order to conserve pins without degradation of the performance of the translation storage controller, this method utilizes the technique of time-multiplexing the address output with itself so that a narrower address path contains, first, the low-order address bits and, then, the high-order bits. In so doing, this technique takes advantage of the fact that the high-order bits must be generated by translation logic. Consequently, there is a natural delay in this translation logic in comparison with the timing of the low-order bits.

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Multiplexed Address on a Translating Storage Controller to Conserve Pins

Certain storage channel controllers have a limitation on the number of available pins.The method described in this article utilizes time multiplexing to conserve pins without adversely affecting performance. In order to conserve pins without degradation of the performance of the translation storage controller, this method utilizes the technique of time-multiplexing the address output with itself so that a narrower address path contains, first, the low-order address bits and, then, the high-order bits. In so doing, this technique takes advantage of the fact that the high-order bits must be generated by translation logic. Consequently, there is a natural delay in this translation logic in comparison with the timing of the low- order bits. Thus, the low-order bits first pass essentially undisturbed through the controller chip to storage, followed by the translation-delayed high-order bits which pass through the same path. The simplified path of a translating storage control unit is illustrated in Fig. 1. As noted, and as shown here, high-order address bits must pass through the translation logic before they are sent to storage. Low-order bits pass virtually undisturbed through the chip to storage; however, for other reasons, they cannot simply bypass the storage controller entirely. A significant delay can be expected through translation logic. This delay is sufficient to allow the low-order, u...