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Improved Queue Management in a Communication Controller

IP.com Disclosure Number: IPCOM000042890D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Ulmer, S: AUTHOR

Abstract

In a communication controller such as represented in the drawing, the the central control unit (CCU) is off-loaded by putting intelligence into the communication scanner processors (CSPs). Particularly when enabling the CSP for a receive operation on the link, the CCU communicates the address of a chain of buffers to the CSP. When data eventually arrive on the link, the CSP transfers the data to the buffers of the CCU through cycle-steal operations. The CSP interrupts the CCU only once when a complete message has been received or when additional buffers are required to hold the complete message.

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Improved Queue Management in a Communication Controller

In a communication controller such as represented in the drawing, the the central control unit (CCU) is off-loaded by putting intelligence into the communication scanner processors (CSPs). Particularly when enabling the CSP for a receive operation on the link, the CCU communicates the address of a chain of buffers to the CSP. When data eventually arrive on the link, the CSP transfers the data to the buffers of the CCU through cycle-steal operations. The CSP interrupts the CCU only once when a complete message has been received or when additional buffers are required to hold the complete message. Thus, either sufficient buffers are pre-allocated to eventually hold the largest message that may arrive much later, in which case these buffers are immobilized and are unproductive while they could be used elsewhere, or an insufficient number of buffers is pre-allocated, in which case additional interrupts to the CCU will be necessary to obtain the missing buffers. Consequently, it is proposed to implement the enqueue and dequeue functions in hardware, both as special instructions in the CCU and in the cycle-steal interface of the I/O bus, in such a way that both hold a global spin lock while updating the queue control block in order to resolve contention. This scheme is applied to a system-free buffer pool. No buffer needs to be pre-allocated to the receive operations, as the CSP can obtain one buffer at a time thr...