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Browse Prior Art Database

CMOS Select 1 of N Multiplexer

IP.com Disclosure Number: IPCOM000042894D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+2]

Abstract

A multiplexer is provided in complementary metal oxide semiconductor (CMOS) technology which selects one of N inputs. As shown in the figure, a multiplexer for selecting one of four input signals A, B, C and D includes field-effect transistors P each having a P channel and field-effect transistors N each having an N channel. It can be seen, e.g., that when selector pulses applied to terminals G1 and G2 are high, the selector pulses applied to terminals G1 and G2 are low and, therefore, input A is selected with the output producing an inverted signal. Likewise, it can be seen that when selector pulses applied to G1 and G2 are high, the selector pulses applied to G1 and G2 are low and, therefore, input C is selected with the output producing an inverted signal. Inputs B and D are selected in a similar manner.

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CMOS Select 1 of N Multiplexer

A multiplexer is provided in complementary metal oxide semiconductor (CMOS) technology which selects one of N inputs. As shown in the figure, a multiplexer for selecting one of four input signals A, B, C and D includes field-effect transistors P each having a P channel and field-effect transistors N each having an N channel. It can be seen, e.g., that when selector pulses applied to terminals G1 and G2 are high, the selector pulses applied to terminals G1 and G2 are low and, therefore, input A is selected with the output producing an inverted signal. Likewise, it can be seen that when selector pulses applied to G1 and G2 are high, the selector pulses applied to G1 and G2 are low and, therefore, input C is selected with the output producing an inverted signal. Inputs B and D are selected in a similar manner. It should be noted that P channel transistors 10 and 12 and N channel transistors 14 and 16 are redundant and may be eliminated, if desired, by connecting node N1 to node N4, node N2 to node N3, node N5 to node N7 and node N6 to node N8. It should also be noted that this multiplexer may be modified to select 1 of N inputs, where N is any integer, by adding or subtracting columns of transistors and the number of transistors in a column depending upon the number of input signals.

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