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High Speed CMOS Latch Circuit

IP.com Disclosure Number: IPCOM000042901D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR

Abstract

A latch circuit is provided in complementary metal oxide semiconductor (CMOS) technolody which does not use standby power, has a minimum number of devices or transistors, and has a very short transition or set. As illustrated in the figure, P channel transistors are identified by a P and N channel transistors are identified by an N. The latch includes transistors 10, 12, 14 and 16, set logic includes transistors 18, 20, 22, 24, 26, 28, 30 and 32, and an output buffer includes transistors 34 and 36. In the operation of the latch circuit, when the data voltage is high at control electrode D1 and the clock pulse is high at control electrode C1 and, thus the voltage being low at C1, transistors 26 and 30 are turned on and node B is at ground.

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High Speed CMOS Latch Circuit

A latch circuit is provided in complementary metal oxide semiconductor (CMOS) technolody which does not use standby power, has a minimum number of devices or transistors, and has a very short transition or set. As illustrated in the figure, P channel transistors are identified by a P and N channel transistors are identified by an N. The latch includes transistors 10, 12, 14 and 16, set logic includes transistors 18, 20, 22, 24, 26, 28, 30 and 32, and an output buffer includes transistors 34 and 36. In the operation of the latch circuit, when the data voltage is high at control electrode D1 and the clock pulse is high at control electrode C1 and, thus the voltage being low at C1, transistors 26 and 30 are turned on and node B is at ground. Since node B is at ground, transistors 10 and 16 of the latch turn on and node B is held at ground potential, with the voltage at the output terminal being high. If the data voltage at D1 is low, node B goes high and the voltage at the output is held low. It can be seen that a data pulse applied to control electrode D2 determines the voltage at the output terminal in a similar manner when the voltage at control electrode C2 is high. It should be noted that improved performance is provided by the use of this latching circuit since the clock and data pulses are directly available to the output buffer without first setting the latch.

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