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Driver Checking Signal Collection Circuit

IP.com Disclosure Number: IPCOM000042904D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Billian, A: AUTHOR [+2]

Abstract

In a data processing system, the data and control bits are placed on bus lines through drivers which have to be checked. The circuit shown in the drawing allows the detection of the driver-induced errors to be made. The circuits driving the lines provide a sense signal. The checking function is performed by a comparison of the input signals of the drivers with their sense signals and by verifying, after a time delay, whether these signals match or not, through XOR circuits. The XOR circuit outputs are ORed to provide an error pulse each time one of the drivers is detected to be in error. The pulse errors are measured in a detriggerable time measurement circuit (DTM), and an error is detected for each pulse error longer than the propagation time in the drivers.

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Driver Checking Signal Collection Circuit

In a data processing system, the data and control bits are placed on bus lines through drivers which have to be checked. The circuit shown in the drawing allows the detection of the driver-induced errors to be made. The circuits driving the lines provide a sense signal. The checking function is performed by a comparison of the input signals of the drivers with their sense signals and by verifying, after a time delay, whether these signals match or not, through XOR circuits. The XOR circuit outputs are ORed to provide an error pulse each time one of the drivers is detected to be in error. The pulse errors are measured in a detriggerable time measurement circuit (DTM), and an error is detected for each pulse error longer than the propagation time in the drivers.

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