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CMOS AOI Circuit Extendible in the or Direction

IP.com Disclosure Number: IPCOM000042905D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Griffin, WR: AUTHOR [+2]

Abstract

A dense AND OR INVERT (AOI) circuit extendible in the OR direction, made in complementary metal oxide semiconductor (CMOS) technology, is provided which has an efficiently structured layout topology. In Fig. 1, an AOI circuit is illustrated wherein field-effect transistors P are P channel transistors and field-effect transistors N are N channel transistors. The basic AOI circuit includes the P channel and N channel transistors having inputs A, B, C and D. This circuit is extended in the OR direction by adding P channel transistors having inputs E and F and also adding N channel transistors having inputs E and F. It can be seen that when inputs A and B or C and D or E and F are up, the output is down. In all other situations the output is up. Thus, the logic function provided by the circuit of Fig.

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CMOS AOI Circuit Extendible in the or Direction

A dense AND OR INVERT (AOI) circuit extendible in the OR direction, made in complementary metal oxide semiconductor (CMOS) technology, is provided which has an efficiently structured layout topology. In Fig. 1, an AOI circuit is illustrated wherein field-effect transistors P are P channel transistors and field- effect transistors N are N channel transistors. The basic AOI circuit includes the P channel and N channel transistors having inputs A, B, C and D. This circuit is extended in the OR direction by adding P channel transistors having inputs E and F and also adding N channel transistors having inputs E and F. It can be seen that when inputs A and B or C and D or E and F are up, the output is down. In all other situations the output is up. Thus, the logic function provided by the circuit of Fig. 1 may be represented by AB + CD + EF. In Fig. 2, there is indicated a topology of the circuit of Fig. 1 wherein the N channel transistors are formed under a ground metal 10 and the P channel transistors are located under a metal power bus 12, with an output line 14 disposed between metal 10 and bus 12 which provides an automated logic methodology. It should be noted that this AOI circuit may be further extended in the same manner to accommodate additional input signals, if desired.

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