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Modular PLA Josephson Decoder

IP.com Disclosure Number: IPCOM000042915D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Beha, H: AUTHOR

Abstract

Combining address register, programmable decode logic and output register in modular fashion provides high speed and multiple fanout capability in a Josephson read-only memory. The modular PLA decoder structure, shown in Fig. 1, comprises three basic blocks: the address register, the programmable decode logic array, and the output register. The address register is used to latch the input address and to provide the true and complement address to the programmable decode logic array. The address register latch circuit, shown in Fig. 1, has the load inductance of the address gates QA mainly determined by the crossing of the inductance of the drive gate Q1AD, resulting in a very short address latch time, which, in addition, is independent of the number n of the address bits.

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Modular PLA Josephson Decoder

Combining address register, programmable decode logic and output register in modular fashion provides high speed and multiple fanout capability in a Josephson read-only memory. The modular PLA decoder structure, shown in Fig. 1, comprises three basic blocks: the address register, the programmable decode logic array, and the output register. The address register is used to latch the input address and to provide the true and complement address to the programmable decode logic array. The address register latch circuit, shown in Fig. 1, has the load inductance of the address gates QA mainly determined by the crossing of the inductance of the drive gate Q1AD, resulting in a very short address latch time, which, in addition, is independent of the number n of the address bits. The programmable decode logic array is realized by using a read- only memory (ROM) array where the ROM cells can be personalized either by a mask step or laser technique. The address signals, activated by øA, run vertically through the ROM array. The word lines, consisting of galvanically connected ROM cells, run horizontally through the ROM-array and control at the end of the array the non-inverting output register gates Q. The decoding function of an n-bit address is implemented by programming all possible Minterms of the ROM array. Therefore, if the applied address matches the stored Minterm, the corresponding output register of the word line is activated. Consequently, each output line realizes the non-function of all input signals that lead to the "1"-programmed ROM cells in the corresponding wordline. A two-bit PLA decoder is shown in Fig. 1 to explain the principle of operation. The driver gates and the output register gates are asymmetric, two-junction interferometers, with two input signals having opposite polarities, as shown in the sketched threshold characteristics in Fig. 2 and the timing shown in Fig. 3. The timing of the PLA decoder is shown in Fig. 4. Note that already in the previous memory cycle, a signal has been launched to activate the driver gates Qw, transferring the currents Iw1 ...Iwi into the wo...