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ADAPTIVE Waveform Relaxation Algorithm

IP.com Disclosure Number: IPCOM000042920D
Original Publication Date: 1984-Jun-01
Included in the Prior Art Database: 2005-Feb-04
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Odeh, FM: AUTHOR [+2]

Abstract

The adaptive waveform relaxation (AWR) algorithm is a new technique for the accurate analysis of large-scale digital circuits. The improvement over the conventional waveform relaxation algorithm and the incremental algorithms is that circuits may much larger, as will be evident. For most circuits the adaptive waveform relaxation approach is not limited by size, provided that sufficient disk space is available. ADAPTIVE STRATEGY The fundamental idea of the adaptive strategy is illustrated by the example of Fig. 1. Here, we assume for simplicity that we have a chain of inverters which exhibit one-way behavior from left to right as shown in Fig. 1. An example of a one-way circuit is a MOSFET transistor where the gate is the input.

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ADAPTIVE Waveform Relaxation Algorithm

The adaptive waveform relaxation (AWR) algorithm is a new technique for the accurate analysis of large-scale digital circuits. The improvement over the conventional waveform relaxation algorithm and the incremental algorithms is that circuits may much larger, as will be evident. For most circuits the adaptive waveform relaxation approach is not limited by size, provided that sufficient disk space is available. ADAPTIVE STRATEGY The fundamental idea of the adaptive strategy is illustrated by the example of Fig. 1. Here, we assume for simplicity that we have a chain of inverters which exhibit one-way behavior from left to right as shown in Fig. 1. An example of a one-way circuit is a MOSFET transistor where the gate is the input. The feedback due to the gate-to-drain capacitance is taken into account with the waveform relaxation (WR) technique. This feedback is shown by the dashed lines in Fig. 1. This feedback is local and weak in most cases. The aim of the adaptive strategy is to avoid having all circuits present in fast memory and to make the exchange of circuits between disk and fast memory as efficient as possible. Thus, we analyze the subcircuits in the following sequence: 1. 1,2,3,4,1,2,3,4,1,2,3,4 until the voltage waveform at node 1 is:

(Image Omitted)

However, we need to do at least three iterations if we want to make sure that the impact of circuit 4 on circuit 1 is observed, as will be discussed below. 2. The waveform n(t) for node 1 is stored, and subcircuit 1 can be discarded. 3. We fetch circuit 5 from disk, analyze 2,3,4,5, and discard circuit 2 after storing its waveform. This technique wi...